Silicon-based thin-film photoelectric conversion device, and method and apparatus for manufacturing the same

A stack-type silicon-based thin-film photoelectric conversion device, comprising:

• a transparent conductive film formed on a substrate;
• and
• a double pin structure stack body;
• said double pin structure stack body being formed of a first p-type semiconductor layer, an i-type amorphous silicon-based photoelectric conversion layer, a first n-type semiconductor layer, a second p-type semiconductor layer, an i-type microcrystalline silicon-based photoelectric conversion layer, and a second n-type semiconductor layer successively formed on said transparent conductive film, and
• each of said first n-type semiconductor layer and said second p-type semiconductor layer having an impurity nitrogen atom concentration not higher than 1×1019 cm−3 and an impurity oxygen atom concentration not higher than 1×1020 cm−3.

A stack-type silicon-based thin-film photoelectric conversion device, comprising:

• a transparent conductive film formed on a substrate;
• and
• a double pin structure stack body;
• said double pin structure stack body being formed of a first p-type semiconductor layer, an i-type amorphous silicon-based photoelectric conversion layer, a first n-type semiconductor layer, a second p-type semiconductor layer, an i-type microcrystalline silicon-based photoelectric conversion layer, and a second n-type semiconductor layer successively formed on said transparent conductive film, and
• concentration of impurity atom determining a conductivity type of said first n-type semiconductor layer being not higher than 3×1019 cm−3 and concentration of impurity atom determining a conductivity type of said second p-type semiconductor layer being not higher than 5×1019 cm−3.

A manufacturing apparatus used for a method of manufacturing a stack-type silicon-based thin-film photoelectric conversion device by forming a double pin structure stack body by successively forming, in an identical plasma CVD film deposition chamber, a first p-type semiconductor layer, an i-type amorphous silicon-based photoelectric conversion layer, a first n-type semiconductor layer, a second p-type semiconductor layer, an i-type microcrystalline silicon-based photoelectric conversion layer, and a second n-type semiconductor layer on a transparent conductive film formed on a substrate, comprising:

• the plasma CVD film deposition chamber where a cathode and an anode are arranged;
• a gas pressure regulating portion regulating a gas pressure within said plasma CVD film deposition chamber;
• and
• an electric power supply portion supplying electric power to said cathode;
• a distance between said cathode and said anode being not smaller than 3 mm and not larger than 20 mm, and
• in forming said first p-type semiconductor layer, said i-type amorphous silicon-based photoelectric conversion layer and said first n-type semiconductor layer, said gas pressure regulating portion being capable of controlling a gas pressure within said CVD film deposition chamber a range from at least 200 Pa to at most 3000 Pa, and said electric power supply portion being capable of controlling power density per unit area of said cathode in a range from at least 0.01 W/cm2 to at most 0.3 W/cm2.

A manufacturing apparatus used for a method of manufacturing a silicon-based thin-film photoelectric conversion device by forming an amorphous pin structure stack body by successively forming, in an identical plasma CVD film deposition chamber, a p-type semiconductor layer, an i-type amorphous silicon-based photoelectric conversion layer, and an n-type semiconductor layer on a transparent conductive film formed on a substrate, comprising:

• the plasma CVD film deposition chamber where a cathode and an anode are arranged;
• a gas pressure regulating portion regulating a gas pressure within said plasma CVD film deposition chamber;
• and
• an electric power supply portion supplying electric power to said cathode;
• a distance between said cathode and said anode being not smaller than 3 mm and not larger than 20 mm, and
• in forming said p-type semiconductor layer, said i-type amorphous silicon-based photoelectric conversion layer and said n-type semiconductor layer, said gas pressure regulating portion being capable of controlling a gas pressure within said CVD film deposition chamber in a range from at least 200 Pa to at most 3000 Pa, and said electric power supply portion being capable of controlling power density per unit area of said cathode in a range from at least 0.01 W/cm2 to at most 0.3 W/cm2.

A manufacturing apparatus used for a method of manufacturing a stack-type silicon-based thin-film photoelectric conversion device by forming a double pin structure stack body by successively forming, in an identical plasma CVD film deposition chamber, a first p-type semiconductor layer, a first i-type amorphous silicon-based photoelectric conversion layer, a first n-type semiconductor layer, a second p-type semiconductor layer, a second i-type amorphous silicon-based photoelectric conversion layer, and a second n-type semiconductor layer on a transparent conductive film formed on a substrate, comprising:

• the plasma CVD film deposition chamber where a cathode and an anode are arranged;
• a gas pressure regulating portion regulating a gas pressure within said plasma CVD film deposition chamber;
• and
• an electric power supply portion supplying electric power to said cathode;
• a distance between said cathode and said anode being not smaller than 3 mm and not larger than 20 mm, and
• in forming said first p-type semiconductor layer, said first i-type amorphous silicon-based photoelectric conversion layer, said first n-type semiconductor layer, said second p-type semiconductor layer, said second i-type amorphous silicon-based photoelectric conversion layer, and said second n-type semiconductor layer, said gas pressure regulating portion being capable of controlling a gas pressure within said CVD film deposition chamber in a range from at least 200 Pa to at most 3000 Pa, and said electric power supply portion being capable of controlling power density per unit area of said cathode in a range from at least 0.01 W/cm2 to at most 0.3 W/cm2.