Compiler implementation of lock/unlock using hardware transactional memory

A compiler comprising:

• a processor core selection unit configured to assign software threads to waiting hardware threads;
• a code generator;
• and
• an optimizer, wherein the optimizer is configured to:
• examine one or more program instructions;
• identify a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory;
• replace the TSR with a first portion of code and a second portion of code;
• and
• set an indication that the first portion of code is to be executed, in response to predicting the TSR will not fail during execution.

A computer readable storage medium storing program instructions operable to parallelize code combined with hardware transactional memory support, wherein the program instructions are executable to:

• examine one or more program instructions;
• identify a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory;
• replace the TSR with a first portion of code and a second portion of code;
• and
• set an indication that the first portion of code is to be executed, in response to predicting the TSR will not fail during execution.