System and method for selecting gates in a logic block
AssigneeSun Microsystems, Inc.
InventorSalim U. Chowdhury
Life of this patent
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Abstract
For each of a plurality of interconnected gates forming one or more non-critical timing paths through a logic block, a gate size may be selected based on (i) a gate delay, (ii) a change in gate delay and gate power associated with downsizing the gate to a next available gate size, and (iii) signal arrival times at one or more inputs and outputs of the gate to minimize power consumed by the logic block while maintaining a specified cycle time.
Claims19
A gate selection system for a logic block comprising:
- one or more computers configured to partition interconnected gates forming a plurality of timing paths into at least two subsets based on gate and interconnect delay of each of the timing paths;
- and
- for each gate of at least one of the subsets, select a gate size based on (i) the gate delay, (ii) a change in gate delay and gate power associated with downsizing the gate to a next available gate size, and (iii) signal arrival times at one or more inputs and outputs of the gate to minimize power consumed by the logic block while maintaining a specified cycle time.
A gate selection method for a logic block comprising:
- for each of a plurality of interconnected gates forming one or more non-critical timing paths through the logic block, electronically selecting a gate size based on (i) a gate delay, (ii) a change in gate delay and gate power associated with downsizing the gate to a next available gate size, and (iii) signal arrival times at one or more inputs and outputs of the gate to minimize power consumed by the logic block while maintaining a specified cycle time.
A computer-readable storage medium having information stored thereon for directing a computer to, for each of a plurality of interconnected gates forming one or more non-critical timing paths through a logic block, select a gate size based on (i) a gate delay, (ii) a change in gate delay and gate power associated with downsizing the gate to a next available gate size, and (iii) signal arrival times at one or more inputs and outputs of the gate to minimize power consumed by the logic block while maintaining a specified cycle time.
Dependencies are inferred from the claim text.