System and method for designing multiple clock domain circuits

A hardware design system that utilizes a hardware description language (HDL) having Term Rewriting System (TRS) rules, the hardware design system comprising:

• a Term Rewriting System Compiler (TRSC) configured to examine a circuit specification and to detect a first module of a first clock domain and to detect a TRS rule of a second clock domain that invoke the first module, the TRSC configured to determine that the first and the second clock domains are of a same clock family;
• and
• the TRSC further configured to automatically generate a new clock signal of the same clock family, the new clock signal gated on if-and-only-if a clock signal of the first clock domain is gated on, the TRSC configured to drive the TRS rule by the new clock signal.

A hardware design system that utilizes a hardware description language (HDL) having Term Rewriting System (TRS) rules, the hardware design system comprising:

• a Term Rewriting System Compiler (TRSC) configured to generate a synchronizer, the synchronizer having ports in both a first clock domain and in a second clock domain, the first clock domain and the second clock domain of different clock families;
• and
• the TRSC further configured to implement a first TRS rule that interfaces with ports of the synchronizer in the first clock domain and configured to implement a second TRS rule that interfaces with ports of the synchronizer in the second clock domain.

A hardware design system for designing a digital circuit, the hardware design system including:

• an HDL to create a circuit specification, the HDL configured to permit specification of a module in a first clock domain and to permit specification of an interface for the module in a second clock domain, the first and second clock domains driven by clock signals that are of different clock families;
• and
• an HDL compiler for use with the circuit specification, the HDL compiler configured to detect the specification of the interface in the second clock domain and automatically instantiate a synchronizer between the module in the first clock domain and the interface in the second clock domain.