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US 2010/0146467 A1Published application
Circuit verification method for verifying circuit with timing information and logic information in library cell
AssigneeNEC Electronics Corporation
InventorHirokazu Hatori
Life of this patent
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Abstract
A circuit verification method propagates a fixed logic value from a black-box circuit block without logic information to a subsequent-stage circuit, by taking into consideration timing information.
Claims8
A circuit verification method executed by a computer, comprising:
- (a) inputting design data relating to a design of a circuit to be verified and a library relating to operation of the circuit to be verified, the library including a logic information concerning the circuit to be verified and a timing information concerning the circuit to be verified;
- (b) setting a fixed logic value for a predetermined node in the circuit to be verified as an initial value;
- (c) tracing the design data from the node for which the fixed logic value is set to select a next-stage circuit block to which the fixed logic value is to be propagated;
- (d) propagating the fixed logic value from an input to an output in the circuit block selected at step (c);
- (e) determining whether or not executable fixed logic value propagation has been completed in all circuit blocks and repeating steps (c) and (d) until the propagation has been completed;
- and
- (f) if the executable fixed logic value propagation has been completed in all circuit blocks, then executing verification of the entire circuit to be verified by using results of the fixed logical value propagation performed by a logic information propagating unit and a timing information propagating unit,
- wherein step (d) comprises:
- (d-1) determining whether or not logic information is defined in a library of the circuit block selected at step (c);
- (d-2) if the logic information is defined in the library, then propagating the fixed logic value from an input of the circuit block to an output of the circuit block on a basis of the logic information;
- and
- (d-3) if the logic information is not defined in the library, then propagating the fixed logic value from the input of the circuit block to the output of the circuit block on a basis of timing information.
9 more elements
A circuit verification apparatus, comprising:
- an input unit which receives design data relating to a design of a circuit to be verified and a library relating to operation of the circuit to be verified;
- a design storage which stores the design data;
- a logic information storage which stores a logic information concerning the circuit to be verified, the logic information being contained in the library;
- a timing information storage which stores a timing information concerning the circuit to be verified, the timing information being contained in the library;
- a fixed logic value setting unit which sets a fixed logic value as an initial value for a predetermined node in the circuit to be verified;
- a next-stage circuit block selecting unit which traces the design data from the node for which the fixed logic value is set to select a next-stage circuit block to which the fixed logic value is to be propagated;
- a library checking unit which determines whether or not logic information is defined in the library of the circuit block selected by the next-stage circuit block selecting unit;
- a logic information propagating unit which propagates a fixed logic value from an input of the circuit block to an output of the circuit block on a basis of the logic information if the logic information is defined in the library;
- a timing information propagating unit which propagates a logic value from an input of the circuit block to an output of the circuit block on a basis of the timing information if the logic information is not defined in the library;
- a propagation completion determining unit which determines whether or not executable fixed logic value propagation has been completed in all circuit blocks;
- and
- a verification executing unit which executes verification of the entire circuit to be verified by using results of propagation of the fixed logic value performed by the logic information propagating unit and the timing information propagating unit when the executable fixed logic value propagation has been completed in all circuit blocks.
9 more elements
Dependencies are inferred from the claim text.