Method for Optimizing and Integerated Circuit Physical Layout
AssigneeTakumi Technology Corpoaration
InventorsMartinus Maria Berkens, Simon Johannes klaver
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Abstract
The invention relates to a method of optimizing an integrated circuit layout, wherein an initial integrated circuit layout is provided. A predetermined set of physical characteristics of a predetermined set of polygons of said initial circuit layout, is assessed and said physical characteristics are aggregated to derive an integral quality number associated to said initial circuit layout. According to the invention, cost functions are generated to evaluate a perturbed quality number of said perturbed layout and layout perturbations are selected that optimize the quality number, so that the circuit layout is optimized.
Claims19
Method of optimizing a global integrated circuit layout comprised of a number of polygons having a predetermined geometrical relation relative to each other, comprising:
- providing an initial global integrated circuit layout;
- assessing local quality numbers, each as a function of a local pattern of shapes in said initial global integrated circuit layout;
- aggregating approximated functions of said local quality numbers, to derive an integral quality number associated to said initial global integrated circuit layout;
- perturbing said integral quality number by varying said initial global integrated circuit layout;
- and
- selecting perturbations that optimize improve the integral quality number, so as to optimize said global integrated circuit layout.
A system for optimizing an integrated circuit layout, comprising:
- an input for receiving an initial global integrated circuit layout;
- a processing circuit arranged to
- assess a function of said initial global integrated circuit layout, to derive an integral quality number associated to said initial circuit layout as an aggregated function of local quality numbers, each as a function of a local pattern of shapes;
- perturb said integral quality number by varying said global integrated circuit layout;
- and
- select perturbations that improve the integral quality number;
- and
- an output for outputting said selected perturbations.
Dependencies are inferred from the claim text.