Performing multi-bit error correction on a cache line

An apparatus comprising:

• a central processing unit, and
• a memory subsystem coupled to the central processing unit, the memory subsystem further comprises a control logic,
• wherein the control logic is to fragment a cache line of a first section of a cache memory into a plurality of segments comprising a first segment and a second segment,
• wherein the memory subsystem further comprises an access logic coupled to the control logic, wherein a first encoder of the access logic is to generate a first set of data bits and a first set of check bits while encoding a first region of a data stream,
• wherein the control logic is to store the first set of data bits in the first segment and the first set of check bits in a first portion of a second section of the cache memory, wherein the first portion is associated with the first segment,
• wherein the memory subsystem further comprises a first decoder, wherein the decoder is to correct errors in multiple bit positions within the first set of data bits using the check bits stored in the first portion of the second section of the cache memory while decoding the first set of data bits.

A machine-readable storage medium comprising a plurality of instructions that in response to being executed result in a processor comprising:

• fragmenting a cache line of a first section of a cache memory into a plurality of segments comprising a first segment and a second segment,
• generating a first set of data bits and a first set of check bits while encoding a first region of a data stream,
• storing the first set of data bits in the first segment and the first set of check bits in a first portion of a second section of the cache memory, wherein the first portion is associated with the first segment, and
• correcting errors in multiple bit positions within the first set of data bits using the check bits stored in the first portion of the second section of the cache memory while decoding the first set of data bits.