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US 2010/0146349 A1Published application
Semiconductor integrated circuit including logic circuit having scan path and test circuit for conducting scan path test
AssigneeNEC Electronics Corporation
InventorMasao Asou
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit is configured which has a logic circuit having scan path flip-flops and a test circuit which executes a scan path test. The test circuit includes a clock control circuit and a scan enable control signal generation circuit. The scan enable control signal generation circuit receives a clock-on information signal output from the clock control circuit and supplies a scan enable control signal to another clock control circuit. The other clock control circuit identifies the value of a scan enable signal on the basis of the scan enable control signal. At this time, the scan path flip-flops output fixed values from data output terminals according to the value of the scan enable signal.
Claims10
A semiconductor integrated circuit comprising:
- a logic circuit having a plurality of scan path flip-flops constituting a scan path;
- and
- a test circuit which executes a scan path test in correspondence with the scan path,
- wherein the test circuit includes:
- a first clock control circuit which controls a scan clock;
- a second clock control circuit;
- and
- a scan enable control signal generation circuit which supplies a scan enable control signal for controlling a scan enable signal, based on a clock-on information signal output from the first clock control circuit,
- wherein the second clock control circuit identifies a value of the scan enable signal on a basis of the scan enable control signal, and
- wherein the scan path flip-flops receive the scan clock and the scan enable signal to output fixed values from data output terminals according to the value of the scan enable signal.
7 more elements
A method of generating a test pattern by a computer, comprising:
- a logic circuit information readout step of reading out a logic circuit information showing a configuration of a logic circuit included in a semiconductor integrated circuit;
- and
- a test pattern generation step of generating a test pattern for testing the semiconductor integrated circuit on a basis of the logic circuit information,
- wherein the test pattern generation step includes:
- (a) generating a test circuit information showing a test circuit which executes a scan test on the logic circuit;
- and
- (b) automatically generating the test pattern on a basis of the test circuit information, and
- the step (a) includes:
- reading out a clock control circuit information showing a clock control circuit which controls a scan clock to be supplied to the logic circuit;
- reading out a scan enable control signal generation circuit information showing a scan enable control signal generation circuit which generates a scan enable control signal for controlling a scan enable signal and supplies the scan enable control signal to the clock control circuit;
- and
- generating the test circuit information on a basis of the clock control circuit information and the scan enable control signal generation circuit information.
9 more elements
A method of testing a semiconductor integrated circuit by a computer, comprising:
- a test pattern generation step of generating a test pattern for testing the semiconductor integrated circuit;
- and
- a test step of executing a scan test on the semiconductor integrated circuit by using the test pattern,
- wherein the test pattern generation step includes:
- (a) generating a test circuit information showing a test circuit which executes a scan test on a logic circuit constituting the semiconductor integrated circuit;
- and
- (b) automatically generating the test pattern on a basis of the test circuit information, and
- the test step includes:
- (c) outputting a clock-on information signal from a clock control circuit which controls a scan clock to be supplied to the logic circuit;
- (d) receiving the clock-on information and generating a scan enable control signal to be supplied to another clock control circuit;
- (e) identifying a value of a scan enable signal for the other clock control circuit on a basis of the scan enable control signal;
- and
- (f) allowing a scan path flip-flop included in the logic circuit to receive the scan clock and the scan enable signal and output a fixed value from a data output terminal according to the value of the scan enable signal.
10 more elements
A method of designing a semiconductor integrated circuit, comprising:
- a logic circuit information readout step of reading out a logic circuit information showing a configuration of a logic circuit included in the semiconductor integrated circuit;
- and
- a test circuit information generation step of generating a test circuit information showing a configuration of a test circuit which executes a scan path test,
- wherein the test circuit information generation step includes:
- (a) reading out a clock control circuit information showing a clock control circuit which controls a scan clock used in the scan path test;
- and
- (b) generating a scan enable control signal generation circuit information showing a scan enable control signal generation circuit which generates a scan enable control signal for controlling a scan enable signal to be supplied to the clock control circuit, and
- the step (b) includes:
- a clock group information generation step of generating, on a basis of the logic circuit information, clock group information by extracting a combination of scan clocks which can be simultaneously applied in one pattern;
- a clock relation information generation step of generating, on a basis of the logic circuit information, clock relation information by extracting a connection relation in the logic circuit necessary for generation of a test pattern;
- and
- a control circuit preparation step of generating the scan enable control signal generation circuit information on a basis of the clock group information and the clock relation information.
9 more elements
Dependencies are inferred from the claim text.