Automated semiconductor design flaw detection system

A method for debugging semiconductor devices, comprising:

• providing a test sequence to a field-programmable gate array (FPGA) implementing a design under test;
• collecting values on inputs and outputs at components within the FPGA in response to the test sequence;
• applying said values on inputs to a model design component, implemented in hardware description language (HDL) code, corresponding to at least a subset of the design under test;
• and
• comparing output of the model design component against the values on outputs observed within the FPGA.

A computer program product comprising a computer readable medium storing instructions that, when executed by a computer processor, cause the processor to:

• provide a test sequence to a field-programmable gate array (FPGA) implementing a design under test;
• collect values on inputs and outputs at components within the FPGA in response to the test sequence;
• apply said values on inputs to a model design component, implemented in hardware description language (HDL) code, corresponding to at least a subset of the design under test;
• and
• compare output of the model design component against the values on outputs observed within the FPGA.

A debug system for semiconductor devices comprising:

• a logic simulator configured to operate a hardware description language (HDL) model, the HDL model comprising:
• a model design component, implemented in HDL code, corresponding to at least a subset of a design under test;
• inputs and outputs corresponding to the inputs and outputs of said design under test;
• a collection module that collects values on inputs and outputs observed within an application-specific integrated circuit (ASIC) implementing the design under test;
• a simulation module that applies said values on inputs to the model design component;
• and
• a comparison module that compares output of the model design component against the values on outputs observed within the ASIC;
• and
• a conversion circuit configured to interface with the ASIC and provide the values on inputs and outputs to the logic simulator.

A debug system for semiconductor devices comprising:

• a logic simulator configured to operate a hardware description language (HDL) model, the HDL model comprising:
• a model design component, implemented in HDL code, corresponding to at least a subset of a design under test;
• inputs and outputs corresponding to the inputs and outputs of said design under test;
• a collection module that collects values on inputs and outputs observed within a semiconductor device implementing the design under test;
• a simulation module that applies said values on inputs to the model design component;
• and
• a comparison module that compares output of the model design component against the values on outputs observed within the semiconductor device;
• and
• a conversion circuit configured to interface with the semiconductor device and provide the values on inputs and outputs to the logic simulator.