Error detection in a multi-processor data processing system
AssigneeFreescale Semiconductor, Inc.
InventorsWilliam C. Moyer, Michael J. Rochford, Davide M. Santo
Life of this patent
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AssigneeFreescale Semiconductor, Inc.
InventorsWilliam C. Moyer, Michael J. Rochford, Davide M. Santo
Estimating the term…
A system and method are provided. The system comprises a first and second processor, and a cross-signaling interface. The first processor executes instructions. The second processor executes the instructions in lockstep with the first processor. The cross-signaling interface is coupled between the first and second processors and is for signaling both an unanticipated altered state a location of the unanticipated altered state in the first processor to the second processor to cause the second processor to emulate the unanticipated altered state in lockstep with the first processor. The method comprises: executing instructions in a first processor; executing the instructions in a second processor in lockstep with the first processor; detecting an error condition in the first processor; transmitting information about the error condition to the second processor; processing the error condition in the first processor; and causing the first and second processor to emulate the error condition in lockstep.
A system comprising:
A method comprising:
The method of claim 10, wherein processing the error condition in the first processor further comprises initiating exception processing in the first processor.
The method of claim 10, wherein processing the error condition in the first processor further comprises initiating a cache control operation in the first processor.
The method of claim 10, wherein transmitting information about the error condition to the second processor further comprises transmitting an error type and a location of the error condition to the second processor.
The method of claim 10, wherein detecting an error in the first processor further comprises detecting a first error in the first processor and a second error in the second processor at the same time, and further comprising determining which of the first error or the second error to process.
In a multi-processor data processing system, a method comprising:
Dependencies are inferred from the claim text.