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US 2010/0146330 A1Published application
Memory device and method thereof
AssigneeAdvanced Micro check here
InventorsSang Dhong, Jin Cho, John Wuu, Gurupada Mandal
Life of this patent
Estimating the term…
Abstract
An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.
Claims20
A device comprising:
- a first bit cell;
- a second bit cell;
- and
- an error correction module coupled to the first bit cell and to the second bit cell to provide corrected data using only information at the first bit cell and the second bit cell in response to a data error at the first bit cell.
1 more element
A method comprising:
- reading a binary logic value stored at a first bit cell;
- reading a binary logic value stored at a second bit cell;
- and
- determining a corrected binary logic value in response to the binary logic value stored at the first bit cell not matching the binary logic value stored at the second bit cell, where the corrected binary logic value is determined by only using the binary logic value stored at the first bit cell and the binary logic value stored at the second bit cell.
1 more element
The method of 12, wherein reading the binary logic value stored at the first bit cell further comprises the first and second thyristors being disposed at respective first and second locations of an integrated circuit that are not adjacent to each other.
Dependencies are inferred from the claim text.