Memory Access Time Measurement Using Phase Detector
AssigneeQUALCOMM Incorporated
InventorsNan Chen, Zhiqin Chen, Varun Verma
Life of this patent
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Abstract
Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews.
Claims21
A method of determining memory access time of a memory, comprising:
- measuring a first phase skew between a first clock signal used by the memory and a second clock signal used as a reference clock signal;
- measuring a second phase skew between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal;
- and
- determining a memory access time of the memory based on the first and second phase skews.
A system configured to determine a memory access time of a memory, comprising:
- means for measuring a first phase skew between a first clock signal used by the memory and a second clock signal used as a reference clock signal;
- means for measuring a second phase skew between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal;
- and
- means for determining a memory access time of the memory based on the first and second phase skews.
A system configured to determine a memory access time of a memory, comprising:
- a first phase detector having first and second inputs, the first input connected to a memory clock signal over a first wired path having a first wire delay and the second input connected to a reference clock signal over a second wired path having a second wire delay;
- a second phase detector having third and fourth inputs, the third input connected to the memory clock signal over a third wired path having a third wire delay and the fourth input connected to the reference clock signal over a fourth wired path having a fourth wired delay, the third wired path including a memory portion that delays the third wired delay;
- a first sampler configured to measure a first phase skew between the memory clock signal over the first wired path and the reference clock signal over the second wired path by indicating when the first and second inputs of the first phase detector are synchronized;
- a second sampler configured to measure a second phase skew between the memory clock signal over the third wired path and the reference clock signal over the fourth wired path by indicating when the third and fourth inputs of the second phase detector are synchronized;
- and
- a processing device configured to determine a memory access time of the memory based on the first and second phase skews.
Dependencies are inferred from the claim text.