US 2010/0146256 A1Published application

Mixed-Mode ROM/RAM Booting Using an Integrated Flash Controller with NAND-Flash, RAM, and SD Interfaces

AssigneeSuper Talent Electronics, Inc.

InventorsJianjun Luo, Chris Tsu, Charles C. Lee, Ming-Shiang Shen

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Abstract

A Secure Digital (SD) flash microcontroller includes a memory interface to SRAM or DRAM, a flash-memory interface, and a SD interface to an SD bus. The flash memory can be on a flash bus or on the SD bus. The microcontroller is booted from boot code stored in the flash memory. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM.

Claims20

Dependent claims

A flash microcontroller comprising:

an input/output interface circuit for establishing communication with a host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting data using a Bulk Only Transport (BOT) protocol;
a flash bus for connecting to a flash-memory chip, the flash bus carrying address, data, and commands to the flash-memory chip;
wherein the flash-memory chip stores first instructions and stores second instructions in a non-volatile memory;
an internal bus coupled to the input/output interface circuit;
a first random-access memory (RAM) for storing first instructions for execution, the first RAM on the internal bus;
a RAM interface to a second RAM for storing second instructions for execution;
wherein the first RAM and the second RAM are volatile memories that lose data when power is removed;
a central processing unit (CPU), on the internal bus, the CPU accessing and executing the first instructions in the first RAM during a first mode and accessing and executing the second instructions in the second RAM during a second mode;
a flash-memory controller, on the internal bus, for generating flash-control signals and for buffering commands, addresses, and data to the flash bus;
a hardwired initializer, activated by a reset signal, for activating the flash-memory controller to read the first instructions from the flash-memory chip, the hardwired initializer writing the first instructions to the first RAM;
a first initialization routine, executed by the CPU while in the first mode after the reset signal is de-asserted, the first initialization routine comprising the first instructions stored in the first RAM;
wherein the first initialization routine activates the flash-memory controller to read the second instructions from the flash-memory chip, the first initialization routine writing the second instructions to the second RAM;
and
a second initialization routine, executed by the CPU while in the second mode, the second initialization routing comprising second instructions stored in the second RAM,
whereby the flash microcontroller is booted from both the first RAM and from the second RAM by the first and second initialization routine.

12 more elements

A method for booting a flash microcontroller comprising:

applying power to the flash microcontroller that is connected to a large random-access memory (RAM);
holding a central processing unit CPU in a reset state after power is applied;
while the CPU is in the reset state, activating a state machine on the flash microcontroller to read an initial boot loader from a first page in a first block of a flash memory coupled to the flash microcontroller by a flash bus;
using the state machine to write the initial boot loader to a small RAM in the flash microcontroller;
releasing the CPU from the reset state, causing the CPU to fetch instructions of the initial boot loader stored in the small RAM;
executing on the CPU the initial boot loader by fetching instructions in the initial boot loader from the small RAM;
reading a next page from the flash memory after the first page and writing the next page to a buffer area of the small RAM as the initial boot loader is executed;
reading the next page from the buffer area of the small RAM and writing the next page to the large RAM as the initial boot loader is executed;
continuing to read next pages from the flash memory and copy the next pages through the buffer area to the large RAM as the initial boot loader is executed until all pages of an extended boot sequence have been copied to the large RAM;
transferring execution from the small RAM to the large RAM;
executing on the CPU the extended boot sequence by fetching instructions in the extended boot sequence from the large RAM;
reading a next page from the flash memory after the extended boot sequence and writing the next page to the buffer area of the small RAM as the extended boot sequence is executed;
reading the next page from the buffer area of the small RAM and writing the next page to the large RAM as the extended boot sequence is executed;
continuing to read next pages from the flash memory and copy the next pages through the buffer area to the large RAM as the extended boot sequence is executed until all pages of a complete boot sequence have been copied to the large RAM;
transferring execution from the extended boot sequence to the complete boot sequence by executing a last instruction in the extended boot sequence that causes the CPU to fetch a first instruction in the complete boot sequence from the large RAM;
and
fetching and executing the complete boot sequence;
establishing communication with a host computer using an input/output interface circuit, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit;
transmitting data using a Bulk Only Transport (BOT) protocol with the input/output interface circuit,
whereby the flash microcontroller is booted by fetching and executing instructions from both the small RAM and from the large RAM.

17 more elements

A multi-interface microcontroller comprising:

input/output interface circuit means for establishing communication with a host computer, wherein the input/output interface circuit means includes a Universal Serial Bus (USB) interface circuit including means for transmitting data using a Bulk Only Transport (BOT) protocol;
flash bus means for connecting to a flash memory, the flash bus means carrying address, data, and commands to the flash memory;
wherein the flash memory stores an initial boot loader, an extended boot sequence, and a complete boot sequence in a non-volatile memory;
first volatile memory means for storing first instructions for execution;
second memory interface means for interfacing to a second volatile memory means for storing second instructions for execution;
processor means, coupled to the input/output interface circuit means, for fetching and executing the first instructions in the first volatile memory means during a first mode and fetching and executing the second instructions from the second volatile memory means during a second mode;
flash-memory controller means for generating flash-control signals and for buffering commands, addresses, and data to the flash bus means;
hardwired initializer means, activated by a reset signal, for activating the flash-memory controller means to read the initial boot loader from the flash memory, and for writing the initial boot loader as the first instructions to the first volatile memory means;
initial boot loader execution means for activating the processor means to fetch and execute the first instructions from the first volatile memory means, the initial boot loader execution means for activating the flash-memory controller means to read the extended boot sequence from the flash memory, and for writing the extended boot sequence as the second instructions to the second volatile memory means;
and
extended boot sequence execution means for activating the processor means to fetch and execute the second instructions from the second volatile memory means, the extended boot sequence execution means for activating the flash-memory controller means to read the complete boot sequence from the flash memory, and for writing the complete boot sequence as additional second instructions to the second volatile memory means.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/651,321Filed 31 Dec 2009
Priority: 6 Jan 2000
Published: 10 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 12/1416
Protection against unauthorised use of memory or access to memory: by checking the object accessibility, e.g. type of access defined by the memory…
G06F 12/0638
Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication: combination of memories, e.g. ROM and RAM…
G06F 21/575
Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates…:…
G06F 21/85
Protecting input, output or interconnection devices: interconnection devices, e.g. bus-connected or in-line devices

Family

Application09/478,720Continuation in part · filed 6 Jan 2000
Application10/789,333Continuation in part · filed 26 Feb 2004
Application11/466,759Continuation in part · filed 23 Aug 2006
Application11/679,716Continuation · filed 27 Feb 2007
Application12/651,321Continuation in part
Application10/789,333Continuation
US 2005/0193161 A1Published application
US 2007/0233955 A1Published application
US 2008/0005471 A1Published application
US 2010/0030961 A9Published application
US 7,257,714 B1Related patent
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US 2010/0146256 A1This patent

From the US filing history. Foreign family members aren’t listed.