Methods and apparatus for performing jump operations in a digital processor

A method for performing a jump operation in a pipelined digital processor having a branch predictor, comprising:

• writing target addresses of jump instructions to be executed by the processor to a memory table;
• providing a jump instruction in an instruction set architecture of the processor, the jump instruction referencing a pointer to a target address in the memory table;
• in response to the branch predictor detecting a first jump instruction, jumping to a first target address;
• and
• modifying the pointer to point to a second target address in the memory table, the second target address corresponding to a second jump instruction.

Apparatus for performing a jump operation in a pipelined digital processor, comprising:

• a memory table to store target addresses of jump instructions to be executed;
• a local memory;
• and
• a jump instruction control unit to control execution of a jump instruction that references a pointer to a target address in the memory table, the jump instruction control unit responsive to a first jump instruction to jump to a first target address, to modify the pointer to point to a second target address in the memory table, to prefetch at least one future target address from the memory table and to write the at least one future target address in the local memory.

A method for performing a jump operation in a pipelined digital processor, comprising:

• writing target addresses of jump instructions to be executed by the processor to a memory table;
• learning a first jump instruction with a branch predictor of the is processor, the first jump instruction referencing a pointer to a first target address in the memory table;
• fetching the first jump instruction with a fetch block of the processor;
• detecting the first jump instruction with the branch predictor;
• reading the first target address corresponding to the first jump instruction from a local memory and providing the first target address to the fetch block of the processor;
• modifying the pointer to point to a second target address in the memory table, the second target address corresponding to a second jump instruction;
• prefetching a future target address from the memory table;
• writing the prefetched future target address to the local memory when the first jump instruction commits;
• and
• retiring the first target address from the local memory when the first jump instruction commits.