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US 2010/0146237 A1Published application
Memory device, memory system, and access timing adjusting method in memory system
AssigneePanasonic Corporation
InventorYuji Takai
Life of this patent
Estimating the term…
Abstract
A memory device (103) includes a memory device controller (140), a delay adjustment storage unit (170) configured to store timing adjustment data which is read as both values 0 and 1 at a rise and a fall of a strobe signal, a memory cell (174), and a selector (172) configured to switch connection to the delay adjustment storage unit or the memory cell. A memory interface (102) reads the timing adjustment data of the delay adjustment storage unit (170) while changing the timing to search for a read timing range, and selects and sets read timing from the timing range.
Claims37
A memory system comprising:
- a memory device;
- a memory interface configured to access the memory device;
- and
- a plurality of data signal lines configured to connect the memory device and the memory interface,
- wherein the memory device includes a memory device controller configured to control an inner portion of the memory device based on access from the memory interface, a memory cell configured to store data, a delay adjustment storage unit configured to store timing adjustment data which is used to adjust timing of data and a strobe signal, and a selector configured to switch a connection target to a path to the memory interface either a path to the delay adjustment storage unit or a path to the memory cell,
- the memory interface reads out both data 0 and 1 at a rise of a strobe signal output from the memory device and both data 0 and 1 at a fall of the strobe signal, as the timing adjustment data, via each of the plurality of data signal lines, and
- the memory interface searches for a timing range within which the data can be read out while changing timing of reading of the timing adjustment data from the delay adjustment storage unit, and selects and sets timing of reading of the data from the timing range.
4 more elements
A memory system comprising:
- a memory device;
- a memory interface configured to access the memory device;
- and
- a command signal line configured to connect the memory device and the memory interface,
- wherein the memory device includes a memory device controller configured to control an inner portion of the memory device based on access from the memory interface, a memory cell configured to store data, a delay adjustment storage unit configured to store timing adjustment data which is used to adjust timing of data and a strobe signal, a data setting unit configured to set the timing adjustment data into the delay adjustment storage unit, and a selector configured to switch a connection target to a path to the memory interface either a path to the delay adjustment storage unit or a path to the memory cell,
- the data setting unit sets data transferred as a command from the memory interface via the command signal line, as the timing adjustment data, into the delay adjustment storage unit, and
- the memory interface reads out the timing adjustment data set in the delay adjustment storage unit while changing the timing to search for a timing range within which the data can be read out, and selects and sets timing of reading of the data from the timing range.
4 more elements
A memory system comprising:
- a memory device;
- a memory interface configured to access the memory device;
- and
- a command signal line configured to connect the memory device and the memory interface,
- wherein the memory device includes a memory device controller configured to control an inner portion of the memory device based on access from the memory interface, a memory cell configured to store data, a data setting unit configured to set data transferred as a command from the memory interface via the command signal line, as timing adjustment data, into the memory cell, and a selector configured to switch a connection target to a path to the memory cell either a path to the data setting unit or a path to the memory interface,
- the memory interface reads out the timing adjustment data set in the memory cell while changing the timing to search for a timing range within which the data can be read out, and selects and sets timing of reading of the data from the timing range.
3 more elements
A method for adjusting access timing in a memory system including a memory device and a memory interface connected to the memory device via a plurality of data signal lines, the method comprising the steps of:
- causing the memory interface to read out both data 0 and 1 at a rise of a strobe signal output from the memory device, and both data 0 and 1 at a fall of the strobe signal, as timing adjustment data, via each of the plurality of data signal lines;
- and
- causing the memory interface to search for a timing range within which data can be read out from the memory cell of the memory device while changing timing of reading of the timing adjustment data, and select and set timing of reading of the data from the timing range.
A method for adjusting access timing in a memory system including a memory device and a memory interface connected to the memory device via a command signal line, the method comprising the steps of:
- causing a data setting unit in the memory device to set data transferred as a command from the memory interface via the command signal line, as timing adjustment data, into a delay adjustment storage unit in the memory device;
- and
- causing the memory interface to read out the timing adjustment data set in the delay adjustment storage unit while changing the timing to search for a timing range within which data can be read out from a memory cell of the memory device, and select and set timing of reading of the data from the timing range.
A method for adjusting access timing in a memory system including a memory device and a memory interface connected to the memory device via a command signal line, the method comprising the steps of:
- causing a data setting unit in the memory device to set data transferred as a command from the memory interface via the command signal line, as timing adjustment data, into a memory cell of the memory device;
- and
- causing the memory interface to read out the timing adjustment data set in the memory cell while changing the timing to search for a timing range within which data can be read out from the memory cell, and select and set timing of reading of the data from the timing range.
A memory device connected to a memory interface via a plurality of data signal lines, comprising:
- a memory cell configured to store data;
- a delay adjustment storage unit configured to store timing adjustment data for outputting both data 0 and 1 at a rise of a strobe signal output from the memory device, and both data 0 and 1 at a fall of the strobe signal, via each of the plurality of data signal lines to the memory interface;
- and
- a selector configured to switch a connection target to a path to the memory interface either a path to the delay adjustment storage unit or a path to the memory cell.
1 more element
A memory device connected to a memory interface via a command signal line, comprising:
- a memory cell configured to store data;
- a delay adjustment storage unit configured to store timing adjustment data used to adjust timing of data and a strobe signal;
- a data setting unit configured to set the timing adjustment data into the delay adjustment storage unit;
- and
- a selector configured to switch a connection target to a path to the memory interface either a path to the delay adjustment storage unit or a path to the memory cell,
- wherein the data setting unit sets data transferred as a command from the memory interface via the command signal line, as timing adjustment data, into the delay adjustment storage unit.
3 more elements
A memory device connected to a memory interface via a command signal line, comprising:
- a memory cell configured to store data;
- a data setting unit configured to set data transferred via the command signal line, into the memory cell;
- and
- a selector configured to switch a connection target to a path to the memory cell either a path to the data setting unit or a path to the memory interface.
1 more element
Dependencies are inferred from the claim text.