Chipset Support For Non-Uniform Memory Access Among Heterogeneous Processing Units

A computer-readable medium storing instructions that, when executed by a processor, cause a computer system to provide a first processor access to a physical memory associated with a second processor included in the computer system, by performing the steps of:

• receiving a first address map from the first processor that includes a memory-mapped input/output (I/O) aperture for a non-uniform memory access (NUMA) device that the first processor is configured to access;
• receiving a second address map from the second processor that includes memory-mapped I/O apertures for a set of hardware devices that the second processor is configured to access;
• generating a global address map by combining the first address map and the second address map;
• receiving a first access request transmitted from the first processor to the NUMA device, whereby the first processor requests access to the physical memory associated with the second processor;
• generating a memory access request based on the first access request and a translation table for translating memory mapped I/O addresses into physical addresses associated with a physical memory, wherein the translation table maps a first address associated with the first access request into a second address associated with the physical memory associated with the second processor;
• and
• routing the memory access request to the physical memory based on the global address map.

A device controller for providing a first processor access to a physical memory associated with a second processor included in a computer system, the device controller comprising:

• a non-uniform memory access (NUMA) device configured to generate a memory access request based on a first access request received from the first processor and a translation table for translating memory mapped input/output (I/O) addresses into physical addresses associated with the physical memory associated with the second processor, wherein the translation table maps a first address associated with the first access request into a second address associated with the physical memory associated with the second processor;
• and
• an input/output (I/O) controller configured to:
• receive a first address map from the first processor that includes a memory-mapped I/O aperture for the NUMA device that the first processor is configured to access;
• receive a second address map from the second processor that includes memory-mapped I/O apertures for a set of hardware devices that the second processor is configured to access;
• generate a global address map by combining the first address map and the second address map;
• receive the first access request transmitted from the first processor to the NUMA device, whereby the first processor requests access to the physical memory associated with the second processor;
• route the memory access request to the physical memory based on the global address map.