System And Method For Maintaining Cache Coherency Across A Serial Interface Bus

A computer-readable medium storing instructions that, when executed by a processor, cause a computing device to determine whether data stored in a memory is valid, by performing the steps of:

• generating a snoop request configured to determine whether first data stored in a local memory coupled to a first processor is coherent relative to second data stored in a data cache coupled to a second processor, the snoop request including:
• destination information that identifies the data cache on a serial interface bus, and
• a cache line address identifying where in the data cache the second data is located;
• causing the snoop request to be transmitted over the serial interface bus to the second processor based on the destination information that identifies the data cache;
• extracting the cache line address from the snoop request;
• determining whether the second data stored in the data cache at the cache line address is coherent relative to the first data stored in the local memory;
• generating a complete (CPL) message that includes:
• destination information that identifies the local memory on the serial interface bus, and
• completion information indicating that the first data is coherent relative to the second data;
• causing the CPL message to be transmitted over the serial interface bus to the first processor based on the destination information that identifies the local memory;
• and
• causing the processing operation to be executed on the first processor using the first data stored in the local memory.

A computer system for determining whether data stored in a memory is valid, comprising:

• a first processor;
• a local memory associated with the first processor;
• a second processor;
• a data cache associated with second processor;
• and
• a serial interface bus configured to route messages between the first processor and the second processor;
• wherein the first processor is configured to:
• generate a snoop request configured to determine whether first data stored in the local memory is coherent relative to second data stored in the data cache, the snoop request including:
• destination information that identifies the data cache on the serial interface bus, and
• a cache line address identifying where in the data cache the second data is located,
• cause the snoop request to be transmitted over the serial interface bus to the second processor based on the destination information that identifies the data cache, and
• execute a processing operation using the first data stored in the local memory;
• and
• wherein the second processor is configured to:
• extract the cache line address from the snoop request,
• determine whether the second data stored in the data cache at the cache line address is coherent relative to the first data,
• generate a complete (CPL) message that includes:
• destination information that identifies the local memory on the serial interface bus, and
• completion information indicating that the first data is coherent relative to the second data, and
• cause the CPL message to be transmitted over the serial interface bus to the first processor based on the destination information that identifies the local memory.