Method and apparatus for combining independent data caches
AssigneeIntellectual Ventures Management, LLC
InventorsDoug Burger, Stephen W. Keckler, Changkyu Kim
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Abstract
Methods, apparatus, computer programs and systems related to combining independent data caches are described. Various implementations can dynamically aggregate multiple level-one (L1) data caches from distinct processors together, change the degree of interleaving (e.g., how much consecutive data is mapped to each participating data cache before addresses go on to the next one) among the cache banks, and retain the ability to subsequently adjust the number of data caches participating as one coherent cache, i.e., the degree of interleaving, such as when the requirements of an application or process change.
Claims19
A method for combining independent data caches comprising:
- providing a plurality of L1 caches associated with a corresponding plurality of processing cores;
- and
- configuring at least two of said plurality of caches that are associated with different cores to operate as a single coherent shared cache.
An apparatus for combining independent data caches comprising:
- a memory system having at least two L1 data caches and at least two processing cores, each of said at least two L1 data caches being associated with a corresponding one of the at least two processing cores;
- and
- a cache configuration manager for configuring at least two of said L1 data caches to operate as a single coherent shared cache.
A multi-core processing arrangement comprising:
- a first processing core comprising a first processor and a first configurable L1 cache that is associated with the first processor;
- a second processing core comprising a second processor and a second configurable L1 cache associated with the second processor, wherein the first configurable L1 cache and the second configurable L1 cache are configured to be shared with one or more of the first processing core and the second processing core;
- an L2 cache operatively coupled to the first and second processing cores and also operatively coupled to the first and second L1 caches, wherein the L2 cache is arranged to store a configuration of the first and second configurable L1 caches.
Dependencies are inferred from the claim text.