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US 2010/0146200 A1Published application
Non-snoop read/write operations in a system supporting snooping
AssigneeIntel Corporation
InventorsAIMEE D. WOOD, Robert J. Safranek
Life of this patent
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Abstract
Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.
Claims19
An apparatus comprising:
- a plurality of point-to-point interfaces to communicate with remote processing entities;
- a plurality of trackers configured to function as a plurality of queues to store non-snoop read and/or non-snoop write operations in order of reception and categorized by associated priority;
- and
- a control circuit coupled with the plurality of trackers to cause the highest priority, non-conflicted non-snoop read/non-conflicted non-snoop write operation to be performed.
1 more element
A system comprising:
- a dynamic random access memory (DRAM)
- a plurality of point-to-point interfaces to communicate with remote processing entities;
- a plurality of trackers configured to function as a plurality of queues to store non-snoop read and/or non-snoop write operations in order of reception and categorized by associated priority;
- and
- a control circuit coupled with the plurality of trackers to cause the highest priority, non-conflicted non-snoop read/non-conflicted non-snoop write operation to be performed utilizing the DRAM.
2 more elements
A method comprising:
- maintaining two or more queues to store posted non-snoop memory access operations, the two or more queues having associated priorities;
- receiving a non-snoop memory access operation;
- determining whether a posted non-snoop memory access operation conflicts with the received non-snoop memory access operation;
- and
- halting processing of at least one higher priority queue in favor of a lower priority queue to resolve the conflict between the posted non-snoop memory access operation and the received non-snoop memory access operation.
2 more elements
An article comprising a computer-readable medium having stored thereon instructions that, when executed, cause one or more processors to:
- maintain two or more queues to store posted non-snoop memory access operations, the two or more queues having associated priorities;
- receive a non-snoop memory access operation;
- determine whether a posted non-snoop memory access operation conflicts with the received non-snoop memory access operation;
- and
- halt processing of at least one higher priority queue in favor of a lower priority queue to resolve the conflict between the posted non-snoop memory access operation and the received non-snoop memory access operation.
2 more elements
Dependencies are inferred from the claim text.