Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips
AssigneeFujitsu Microelectronics Limited
InventorYOSHIHIRO TAKEMAE
Life of this patent
Estimating the term…
Abstract
A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
Claims11
1-21. (canceled)
A multi chip package comprising:
- a system LSI chip including a common memory controller capable of controlling chips including a respective memory among different types of memories operating with different specifications,
- the common memory controller comprising:
- a first interface portion that receives a control output signal to access the chips from a controller, and outputs a control input signal to the controller;
- a second interface portion that outputs a memory input signal through a common bus terminal portion coupled to the chips and receives the memory output signal through the common bus terminal portion;
- an operation memory that outputs a first control signal including specifications of the memories;
- an arbiter that outputs a second control signal and a third control signal;
- a conversion control portion that converts the control output signal into the memory input signal in response to at least one of the first control signal and the second control signal, and converts the memory output signal respectively into the control input signal;
- and
- a signal holder that holds the controller output signals in response to at least one of the third control signal and a fourth control signal from the conversion control portion,
- wherein the memory input signal includes a first memory input signal corresponding to a first memory and a second memory input signal corresponding to a second memory, type of which is different from the type of the first memory.
A multi chip package comprising:
- a system LSI chip including a common memory controller capable of controlling chips including a respective memory among different types of memories operating with different specifications, the chips including a first chip and a second chip;
- a controller for outputting controller output signals to access the chips;
- a memory controller for converting the controller output signals into memory input signals according to command specifications for accessing the respective chips, and converting memory output signals output from the chips into controller input signals receivable to the controller;
- and
- a common bus for connecting the first chip, the second chip and the memory controller to transmit the memory input signals and the memory output signals,
- wherein the command specifications for the first chip and the second chip are different so that the memory input signals of the first chip and the second chip are different, and
- wherein the system LSI chip, the first chip and the second chip are stacked in three dimensions, the system LSI chip, the first chip and the second chip include at least one hole in a peripheral area and the hole of the first chip couples to the hole of the second chip via interconnection wiring.
Dependencies are inferred from the claim text.