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US 2010/0146187 A1Published application
Endurance management technique
OwnerKnut S. Grimsrud, Richard L. Coulsoninventors
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Abstract
According to embodiments of the present invention, endurance management techniques are disclosures. Adherence to endurance and data retention ratings are ensured by managing write accesses to a memory device.
Claims19
A method comprising:
- tracking a magnitude of write cycles accessing a memory;
- throttling additional write accesses to the memory when the magnitude of write cycles approaches a total write threshold that changes with time, wherein the throttling produces a gradual decrease in write performance of the memory.
An apparatus comprising:
- a memory array;
- a host interface for receiving access requests to the memory array from a host;
- memory management functionality that produces write access requests to the memory array;
- and
- a controller for controlling accesses to the memory array from the host interface and the memory management functionality, the controller configured to:
- track a magnitude of write cycles accessing the memory array;
- and
- throttle additional write accesses to the memory array when the magnitude of write cycles approaches a total write threshold that changes with time, wherein throttling additional write accessing produces a gradual decrease in write performance of the memory array.
5 more elements
A system comprising:
- a memory array;
- a host that generates access requests to the memory array, the host comprising a processor and one or more input/output interfaces;
- memory management functionality that produces write access requests to the memory array;
- and
- a controller for controlling accesses to the memory array from the host and the memory management functionality, the controller configured to:
- track a magnitude of write cycles accessing the memory array;
- and
- throttle additional write accesses to the memory array when the magnitude of write cycles approaches a total write threshold that changes with time, wherein throttling additional write accessing produces a gradual decrease in write performance of the memory array.
5 more elements
Dependencies are inferred from the claim text.