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US 2010/0146178 A1Published application
Negation-based fixed-priority arbiter
OwnerDaaven Shawn Messingerinventor
Life of this patent
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Abstract
A device includes an M-bit input request for service bus, a NEGATE component that may perform a negation operation on the M-bit input bus, an AND component that may perform a Boolean AND operation on the M-bit input signal and the negated input, and an M-bit 1-HOT grant output bus that indicates which request for service is being granted.
Claims10
A device comprising:
- an input bus that includes M bits, where the input bus is to receive an M-bit signal that includes one or more requests for service;
- a NEGATE component that is to perform a negation operation on the M-bit input signal and to output a negated input signal;
- an AND component that is to perform a Boolean AND operation on the M-bit input signal and the negated input signal;
- and
- an output bus that includes M bits, where the output bus is to generate an 1-HOT encoded M-bit output signal that indicates a particular request for service, from the one or more requests for service, is being granted.
2 more elements
A method, performed by an electronic device, comprising:
- receiving an M-bit signal that includes one or more requests for service;
- negating the M-bit input signal to generate a negated input signal;
- combining the M-bit input signal and the negated input signal using an AND operation to generate a combined signal;
- and
- generating a 1-HOT encoded M-bit output signal that indicates a particular request for service, from the one or more requests for service, is being granted, the generating being based on the combined signal.
2 more elements
Dependencies are inferred from the claim text.