Apparatus and Method for Controlling a Master/Slave System via Master Device Synchronization
AssigneeRambus Inc.
InventorStefanos Sidiropoulos
Life of this patent
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Abstract
A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave device to the master device in accordance with the master receive data phase value. The master device characterizes a master transmit data phase value to coordinate the transfer of data from the master device to the slave device. Subsequently, the master device routes data to the slave device in accordance with the master transmit data phase value.
Claims22
A method for use with a memory system having a memory controller and a memory device coupled together by a data bus and by a request bus, the method comprising:
- receiving data at the memory device transmitted by the memory controller over the request bus;
- rerouting in the memory device the data received over the request bus to a data bus output buffer as rerouted data;
- and
- transmitting the rerouted data from the memory device to the memory controller over the data bus.
A memory system, comprising:
- a memory controller;
- a memory device;
- a request bus coupling the controller and the memory device, wherein the request bus is configured to carry control signals;
- and
- a data bus coupling the controller and the memory device, wherein the data bus is configured to carry data signals;
- wherein the memory device includes circuitry configured to:
- selectively reroute data received from the memory controller over the request bus to a data bus output buffer as rerouted data;
- and
- transmit the rerouted data to the memory controller over the data bus.
A memory device for use in a system including a memory controller, a request bus coupling the memory controller and the memory device, and a data bus coupling the memory controller and the memory device, the memory device comprising:
- a data bus output buffer;
- circuitry configured to selectively reroute data received from the memory controller over the request bus to the data bus output buffer as rerouted data;
- and
- a timing circuit configured to time outputs from the data bus output buffer to the memory controller.
Dependencies are inferred from the claim text.