Floating-point fused add-subtract unit
AssigneeCrossfield Technology LLC
InventorsEarl E. Swartzlander, JR., Hani H. Saleh
Life of this patent
Estimating the term…
Abstract
In a particular embodiment, a method is disclosed that includes receiving first and second operands at a floating-point fused add-subtract circuit. The method further includes simultaneously performing add and subtract operations on the first and second operands via the floating-point fused add-subtract circuit to produce a sum result output and a difference result output. The floating-point fused add-subtract circuit includes sign logic, exponent adjustment logic, and shift logic that are shared by an add/round and post-normalize circuit and a subtract/round and post-normalize circuit to produce the sum and difference result outputs.
Claims20
A method comprising:
- receiving first and second operands at a floating-point fused add-subtract circuit;
- and
- simultaneously performing add and subtract operations on the first and second operands via the floating-point fused add-subtract circuit to produce a sum result output and a difference result output;
- wherein the floating-point fused add-subtract circuit includes sign logic, exponent adjustment logic, and shift logic that are shared by an add/round and post-normalize circuit and a subtract/round and post-normalize circuit to produce the sum and difference result outputs.
A circuit device comprising:
- a first input to receive a first operand;
- a second input to receive a second operand;
- sign logic to receive sign bits associated with the first and second operands and to determine first and second sign output values;
- exponent difference and select logic to receive exponent bits from the first and second operands and to determine an exponent adjustment value and a shift control signal;
- first and second 2:1 multiplexers to select from the first and second operands to produce first and second values;
- a shift circuit adapted to shift the second value based on the shift control signal;
- an add/round and post-normalize circuit to add first value and the shifted second value to produce a sum and to round and normalize the sum to produce a sum output;
- a subtract/round and post-normalize circuit to subtract the first value and the shifted second value to produce a difference and to round and normalize the difference to produce a difference output;
- logic to combine the first sign output value and the sum output to produce a sum result at a first output and to combine the second sign output value and the difference output to produce a difference result at a second output.
A fused add-subtract unit comprising:
- first and second multiplexers to receive first and second operands and to produce a first value and a second value;
- an add/round and post-normalize circuit to add the first value and a shifted value related to the second value to produce a sum and to round and normalize the sum to produce a sum result;
- a subtract/round and post-normalize circuit to subtract the shifted value from the first value to produce a difference and round and normalize the difference to produce a difference result;
- an exponent difference and select circuit to receive first and second exponents from first and second operands and to determine an exponent comparison value and an exponent output value;
- sign logic to receive first and second sign bits of first operand and second operands and to produce a sum sign and a difference sign based on the first and second sign bits and an exponent comparison value;
- and
- an exponent adjust circuit to receive the exponent output value and to produce a sum exponent and a difference exponent.
Dependencies are inferred from the claim text.