US 2010/0144117 A1Published application

Semiconductor device having device characteristics improved by straining surface of active region and its manufacture method

AssigneeFujitsu Limited

InventorsSadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh

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Abstract

A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

Claims8

Dependent claims

A method of manufacturing a semiconductor device comprising:

(a) forming a trench in a surface layer of a semiconductor substrate, the trench surrounding an active region;
(b) depositing a lower insulating film made of insulating material over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region;
(c) depositing an upper insulating film made of insulating material having therein a tensile stress on the lower insulating film, the upper insulating film filling the empty space left in the upper space;
and
(d) removing the upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/708,519Filed 18 Feb 2010
Priority: JP 2006-09470430 Mar 2006
Published: 10 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 62/405
Crystalline structures: orientations of crystalline planes
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/795
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in lateral device isolation regions, e.g. STI

Family

Application11/541,782Division · filed 3 Oct 2006
Application12/708,519Division
US 2007/0228488 A1Published application
US 7,701,016 B2Related patent
US 7,951,686 B2Related patent
US 2010/0144117 A1This patent

From the US filing history. Foreign family members aren’t listed.