Semiconductor Memory Device

A method of fabricating a memory device, the method comprising;

• forming a semiconductor substrate having a first surface;
• forming a recessed gate in the substrate, wherein the recessed gate defines a first and second lateral sides;
• forming a first source/drain region on the first surface of the semiconductor substrate adjacent a first lateral side of the recessed gate;
• forming a second source/drain region on the first surface of the semiconductor substrate adjacent a second lateral side of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate;
• forming a charge storage device above the semiconductor substrate, wherein the charge storage device is electrically coupled to the first source/drain region;
• and
• forming a conductive data line between the charge storage device and the first surface of the semiconductor substrate, wherein the conductive data line comprises a first portion that extends a first height above the first surface of the semiconductor substrate and a second portion that extends downward from the first portion to electrically and physically contact the second source/drain region, and wherein the first and second portions are formed of the same material.

A method of fabricating a memory device, the method comprising;

• forming a semiconductor substrate having a first surface;
• forming a recessed gate in the substrate, wherein the recessed gate defines first and second lateral sides;
• forming a first source/drain region on the first surface of the semiconductor substrate adjacent a first lateral side of the recessed gate;
• forming a second source/drain region on the first surface of the semiconductor substrate adjacent a second lateral side of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate;
• depositing dielectric material over the recessed gate and the second source/drain region;
• forming a charge storage device above the semiconductor substrate, wherein the charge storage device is electrically coupled to the first source/drain region;
• forming a contact hole through the dielectric material to expose the second source/drain region;
• depositing conductive material into the contact hole and forming a conductive data line between the charge storage device and the first surface of the semiconductor substrate with the conductive material, wherein the conductive data line comprises a first portion that extends a first height above the first surface of the semiconductor substrate and a second portion that extends downward from the first portion to electrically and physically contact the second source/drain region, and wherein the first and second portions are formed of said conductive material deposited into the contact hole.