Methods for fabricating stressed mos devices
AssigneeAdvanced Micro Devices, Inc.
InventorsAndrew M. Waite, Andy C. Wei
Life of this patent
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Abstract
Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.
Claims20
A method for fabricating a MOS device, the method comprising the steps of:
- providing a silicon substrate having a P-well region;
- depositing a polycrystalline silicon gate electrode layer overlying the P-well region of the silicon substrate;
- implanting P-type dopant ions into the polycrystalline silicon gate electrode layer to form a P-type implanted region;
- forming a first polycrystalline silicon gate electrode overlying the P-well region of the silicon substrate;
- etching recesses into the P-well region of the silicon substrate using the first polycrystalline silicon gate electrode as an etch mask, wherein the step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide;
- and
- forming a tensile stress-inducing material within the recesses.
A method for fabricating a CMOS device, the method comprising the steps of:
- depositing a polycrystalline silicon gate electrode layer overlying a silicon substrate having a P-well region and N-well region;
- implanting P-type dopant ions into the polycrystalline silicon gate electrode layer to form a P-type implanted region;
- etching the polycrystalline silicon gate electrode layer to form an NMOS gate electrode overlying the P-well region and a PMOS gate electrode overlying the N-well region;
- forming sidewall spacers about the NMOS gate electrode and the PMOS gate electrode;
- implanting N-type impurity dopants into the P-well region using the NMOS gate electrode and the sidewall spacers as an implantation mask to from source and drain regions of an NMOS transistor;
- implanting P-type impurity dopants into the N-well region using the PMOS gate electrode and the sidewall spacers as an implantation mask to from source and drain regions of a PMOS transistor;
- etching recesses into the P-well region using the NMOS gate electrode and the sidewall spacers as an etch mask, wherein the step of etching is performed by exposing the P-well region to tetramethylammonium hydroxide;
- and
- forming a tensile stress-inducing material in the recesses.
Dependencies are inferred from the claim text.