High Throughput Die-to-Wafer Bonding Using Pre-Alignment
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWen-Chih Chiou, Weng-Jin Wu, Chen-Hua Yu
Life of this patent
Estimating the term…
Abstract
A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action.
Claims17
A method of forming integrated circuits, the method comprising:
- providing a bottom wafer comprising a plurality of bottom dies;
- aligning a first top die with a first bottom die in the bottom wafer;
- recording a first destination position of the first top die after the first top die is aligned with the first bottom die;
- bonding the first top die onto the first bottom die;
- calculating a second destination position of a second top die using the first destination position;
- moving the second top die to the second destination position;
- and
- bonding the second top die onto a second bottom die without any additional alignment action.
A method of forming integrated circuits, the method comprising:
- providing a bottom wafer comprising bottom dies;
- placing top dies into die holders of a die tray;
- placing the die tray adjacent to the bottom wafer, with an X-axis of the die tray being parallel to an X-axis of the bottom wafer;
- picking up and aligning a first top die to a first bottom die in the bottom wafer;
- recording coordinates of the first top die;
- bonding the first top die onto the first bottom die;
- calculating a position of a second top die to be moved according to the coordinates, wherein the position of the second top die corresponds to a second bottom die in the bottom wafer;
- and
- bonding the second top die to the second bottom die without an action for aligning the second top die to the second bottom die.
A method of forming integrated circuits, the method comprising:
- placing top dies comprising a first top die and a second top die into die holders of a die tray;
- placing the die tray adjacent to a bottom wafer, with an X-axis of the die tray being parallel to an X-axis of the bottom wafer;
- determining a relative x-coordinate and a relative y-coordinate of a second bottom die in the bottom wafer relative to a first bottom die in the bottom wafer;
- picking up and aligning the first top die with the first bottom die in the bottom wafer;
- recording a first x-coordinate and a first y-coordinate of the first top die after the first top die is aligned with the first bottom die;
- bonding the first top die onto the first bottom die;
- calculating a second x-coordinate by adding the first x-coordinate and the relative x-coordinate, and a second y-coordinate by adding the first y-coordinate and the relative y-coordinate;
- moving the second top die from the die tray to a second position corresponding to the second x-coordinate and the second y-coordinate;
- and
- bonding the second top die onto the second bottom die.
Dependencies are inferred from the claim text.