US 2010/0142702 A1 · Kasumi Cipher Executable Instructions and Circuitry

Abstract

Logic circuitry and corresponding software instructions for performing functions within the FL function of a Kasumi cipher. An RLAX logic circuit includes a bit-wise AND function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLAX program instruction. An RLOX logic circuit includes a bit-wise OR function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLOX program instruction. Plural instances of the logic circuits can be implemented in parallel, to simultaneously operate upon plural data blocks.

Claims23

Dependent claims

Programmable digital logic circuitry, comprising:

program memory for storing a plurality of program instructions arranged in a sequence, the plurality of program instructions comprising a first program instruction corresponding to an RLAX function of a first and a second operand, the RLAX function returning a value corresponding to a data word having a first portion corresponding to a first portion of the first operand, and a second portion corresponding to the result of a sequence of operations comprising:
performing a bit-wise AND function of the first portion of the first operand and a first portion of the second operand;
then performing a one-bit left rotate of the result of the bit-wise AND function;
and
then performing a bit-wise exclusive-OR of the result of the one-bit left rotate and the second portion of the first operand;
a register bank comprising register locations for storing the operands and the returned value;
and
a first logic circuit for executing the first program instruction upon the first and second operands stored in the register bank.

5 more elements

Programmable digital logic circuitry, comprising:

program memory for storing a plurality of program instructions arranged in a sequence, the plurality of program instructions comprising a first program instruction corresponding to an RLOX function of a first and a second operand, the RLOX function returning a value corresponding to a data word having a first portion corresponding to a first portion of the first operand, and a second portion corresponding to the result of a sequence of operations comprising:
performing a bit-wise OR function of the second portion of the first operand and a second portion of the second operand;
then performing a one-bit left rotate of the result of the bit-wise OR function;
and
then performing a bit-wise exclusive-OR of the result of the one-bit left rotate and a first portion of the first operand;
a register bank comprising register locations for storing the operands and the returned value;
and
a first logic circuit for executing the first program instruction upon the first and second operands stored in the register bank.

5 more elements

Dependencies are inferred from the claim text.

Kasumi Cipher Executable Instructions and Circuitry

Life of this patent

Kasumi Cipher Executable Instructions and Circuitry

Life of this patent

Abstract

Claims23