Hardware implementation of network testing and performance monitoring in a network device
AssigneeMarvell Israel (M.I.S.L) Ltd.
InventorsNir Arad, Tsahi Daniel, Maxim Mondaeev
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Abstract
An embodiment of the present invention offloads the generation and monitoring of test packets from a Central processing Unit (CPU) to a dedicated network integrated circuit, such as a router, bridge or switch chip associated with the CPU. The CPU may download test routines and test data to the network IC, which then generates the test packets, identifies and handles received test packets, collects test statistics, and performs other test functions all without loading the CPU. The CPU may be notified when certain events occur, such as when throughput or jitter thresholds for the network are exceeded.
Claims1
A method of generating payload data for a plurality of test packets to be transmitted by an integrated circuit, the method comprising:
- planting a set of data to a buffer allocated to supply payload data for the plurality of test packets;
- reading the planted set of data from the buffer for use as payload data in a first test packet;
- reading the planted set of data from the buffer for use as payload data in a second test packet;
- processing a plurality of data packets received by the integrated circuit to determine forwarding information for the plurality of data packets;
- and
- transmitting the first test packet, the second test packet, and one or more data packets of the plurality out of the integrated circuit directed to a network.
Dependencies are inferred from the claim text.