Semiconductor memory device and testing method therefor
AssigneeElpida Memory, Inc.
InventorYuki HOSOE
Life of this patent
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Abstract
A semiconductor memory device includes memory blocks, a redundancy determining circuit that can enter in a parallel test mode in which the both memory blocks are simultaneously accessed, and a verifying circuit that verifies data read from the memory blocks. When accessing normal cell areas of the memory blocks simultaneously, in response to a fact that at least one of the memory blocks is replaced by a redundancy memory cell, the redundancy determining circuit supplies pass signals indicating a memory block in which replacement is performed to the verifying circuit. Based on the pass signals, the verifying circuit passes verification of data read from the memory block in which the replacement is performed.
Claims7
A semiconductor memory device comprising:
- a first memory block and a second memory block each including a normal cell area having a plurality of normal memory cells and a redundancy cell area having a plurality of redundancy memory cells for replacing a defective memory cell among the normal memory cells;
- a redundancy determining circuit that can enter at least a normal operation mode in which either one of the first and second memory blocks is accessed and a parallel test mode in which both the first and second memory blocks are simultaneously accessed;
- and
- a verifying circuit that verifies data read from the first and second memory blocks in the parallel test mode, wherein
- the redundancy determining circuit supplies the verifying circuit with a pass signal in response to a fact that a replacement from the normal memory cell to be accessed with the redundancy memory cell is performed in at least one of the first and second memory blocks when accessing the normal cell areas of the first and second memory blocks simultaneously in the parallel test mode, and
- the verifying circuit passes verification of data read from the normal cell area of the memory block in which the replacement is performed and exclusively performs verification of data read from the normal cell area of the memory block in which replacement is not performed based on the pass signal.
A testing method of a semiconductor memory device that includes a first memory block and a second memory block each having a normal cell area having a plurality of normal memory cells and a redundancy cell area having a plurality of redundancy memory cells for replacing a defective memory cell among the normal memory cells, the method comprising:
- accessing the normal cell areas of the first and second memory blocks simultaneously;
- and
- verifying data read from the first and second memory blocks, wherein
- if the normal memory cell to be accessed is replaced with the redundant memory cell in at least one of the first and second memory blocks, verifying is passed with respect to a memory block in which a replacement is performed, and exclusively verifying the read data with respect to a memory block in which a replacement is not performed.
Dependencies are inferred from the claim text.