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US 2010/0142301 A1Published application
Semiconductor memory device and self refresh test method
AssigneeNEC Electronics Corporation
InventorsShinya TASHIRO, Koichiro SUGA
Life of this patent
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Abstract
A semiconductor memory device includes a memory cell array that includes a plurality of memory cells, an SR timer that determines a cycle of self refresh of the memory cell, a refresh counter that generates an internal address signal of the memory cell which is a target of the self refresh, and a circuit that outputs a pulse active signal to continuously execute refresh operation in one cycle of the self refresh.
Claims15
A semiconductor memory device comprising:
- a memory cell array that comprises a plurality of memory cells;
- an SR timer that determines a cycle of self refresh of the memory cell;
- a refresh counter that generates an internal address signal of the memory cell which is a target of the self refresh;
- and
- a circuit that outputs a pulse active signal to continuously execute refresh operation in one cycle of the self refresh.
2 more elements
A test method of a memory cell array that comprises a plurality of memory cells, the method comprising:
- determining a cycle of self refresh;
- generating an internal address signal of the memory cell which is a target of the self refresh;
- and
- continuously performing refresh operation in one cycle of the self refresh.
1 more element
Dependencies are inferred from the claim text.