Semiconductor memory device and delay locked loop control method thereof

A semiconductor memory device, comprising:

• a division circuit configured to divide an input clock to output a divided clock during a specific mode;
• an oscillation circuit configured to count the divided clock to output an oscillation signal;
• a control circuit configured to output a delay locked loop (DLL)-on signal in response to the oscillation signal;
• and
• a DLL circuit configured to delay and lock an external clock to generate a DLL clock, and to be turned on in response to the DLL-on signal during the start of the specific mode.

A method for controlling a delay locked loop (DLL), comprising:

• dividing a clock to output a divided clock during a specific mode where a DLL circuit is maintained in a turn-off state;
• counting the divided clock to output an oscillation signal;
• and
• outputting a DLL on signal which is periodically activated in synchronization with the divided clock by using the oscillation signal,
• wherein the DLL circuit is periodically turned on by the DLL-on signal during the specific mode.

A semiconductor memory device, comprising:

• an oscillation signal generating circuit configured to divide an input clock to output an oscillation signal.
• a control circuit configured to output a delay locked loop (DLL)-on signal in response to the oscillation signal;
• and
• a DLL circuit configured to delay and lock an external clock to generate a DLL clock, and to be turned on in response to the DLL-on signal during the start of the specific mode.