Vertical Transistor Memory Cell and Array

A semiconductor device comprising:

• a gate;
• a body region configured as an electrically floating body, the body region configured so that material forming the body region extends beyond at least one vertical boundary of the gate;
• and
• a source region and a drain region adjacently disposed to the body region in opposing planes.

A transistor comprising:

• a source region disposed on an insulating substrate;
• a floating body region disposed over the source region;
• a drain region disposed over the floating body region and opposing the source region;
• and,
• a gate encompassing the floating body region and a portion of one or more of the source region and drain region, wherein a doping profile of one or more of the source and the drain region is configured to prevent formation of a contiguous current channel extending between the source region and the drain region through the floating body region.

A method for forming a transistor, comprising:

• forming a source region by implanting an impurity into a first portion of a semiconductor;
• forming a floating body region over the source region, wherein the floating body includes a pillar structure and defines a vertical channel;
• forming an insulating layer and a gate to encompass the floating body region, wherein the insulating layer is disposed between the gate and the floating body region;
• and,
• forming a drain region by implanting the impurity into a second portion of the semiconductor adjacent to the floating body region, wherein the drain region is formed to oppose the source region vertically.

An integrated circuit device comprising:

• a memory cell including a transistor, the transistor comprising,
• a body region configured to be electrically floating;
• a gate disposed about a first boundary of the body region;
• a drain region adjoining a second boundary of the body region, the second boundary adjacent the first boundary and separating the drain region from the first boundary;
• and,
• a source region vertically separated from the drain region and adjoining a third boundary of the body region, the third boundary adjacent the first boundary and separating the source region from the first boundary;
• wherein the memory cell includes a first data state representative of a first charge in the body region, wherein the memory cell includes a second data state representative of a second charge in the body region;
• wherein first write control signals can be applied to the memory cell to write the first data state and second write control signals to the memory cell to write the second data state, wherein, in response to first write control signals, the electrically floating body transistor generates a first source current which substantially provides the first charge in the body region.

An integrated circuit device comprising:

• a memory cell array including a,
• plurality of word lines;
• plurality of source lines;
• plurality of bit lines;
• and
• plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes a transistor comprising,
• a body region configured to be electrically floating;
• a gate disposed about a first boundary of the body region, the gate coupled to an associated word line;
• a drain region adjoining a second boundary of the body region, the second boundary adjacent the first boundary and separating the drain region from the first boundary, the drain region coupled to an associated bit line;
• and,
• a source region vertically separated from the drain region and adjoining a third boundary of the body region, the third boundary adjacent the first boundary and separating the source region from the first boundary, the source region coupled to an associated source line;
• wherein each memory cell includes a first data state representative of a first charge in the body region, wherein each memory cell includes a second data state representative of a second charge in the body region;
• wherein the drain region of each memory cell of a first column of memory cells is connected to a first bit line,
• wherein the source region of each memory cell of a first row of memory cells is connected to a first source line;
• wherein, in response to first write control signals applied to at least a portion of the memory cells of the first row of memory cells, the electrically floating body transistor of each memory cell of the portion of the memory cells of the first row of memory cells generates a first source current which at least substantially provides the first charge in the body region of the electrically floating body transistor of the portion of the memory cells of the first row of memory cells.