Nonvolatile semiconductor memory and method for testing the same

Abstract

A nonvolatile semiconductor memory includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a trimming code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a trimming code output circuit that outputs any one of plural trimming codes to the voltage generator circuit. The plural trimming codes include a test trimming code in addition to an appropriate trimming code for generating a desired drive voltage. The test trimming code is different from the appropriate trimming code, and used only in the test state. In the test state, the trimming code output circuit outputs the test trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the test trimming code. In states other than the test state, the trimming code output circuit outputs the appropriate trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the appropriate trimming code.

Dependencies are inferred from the claim text.