Reducing read failure in a memory device
AssigneeMicron Technology, Inc.
InventorsSeiichi Aritome, Alessandro Torsi, Carlo Musilli
Life of this patent
Estimating the term…
Abstract
Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.
Claims20
A method for reducing read failure in a memory device comprising a memory array having a drain side and a source side and a plurality of word lines, each coupled to a row of memory cells, between the drain side and the source side, the method comprising:
- determining proximity of a word line of memory cells to be erased to the drain side of the memory array;
- and
- varying a depth of erasure of the word line of memory cells in response to the proximity to the drain side.
A method for reducing read failure in a memory device comprising a memory array having a drain side and a source side and a plurality of word lines, each coupled to a row of memory cells, between the drain side and the source side, the method comprising:
- determining proximity of a word line of memory cells to be erased to the drain side of the memory array;
- and
- erasing word lines of memory cells that are closer to the drain side to a lower threshold voltage than word lines of memory cells that are closer to the source side.
A memory device comprising:
- a memory array comprised of a plurality of memory cells arranged in memory blocks having rows and columns, each row coupled to a word line and each column coupled to a bit line, the memory array further comprising a drain side and a source side;
- and
- a memory control circuit coupled to the memory array for controlling an erase operation of a memory block of the memory device, the control circuit configured to erase to a lower threshold voltage memory cells coupled to word lines that are closer to the drain side than memory cells coupled to word lines that are closer to the source side.
A method for reducing read failure in a memory device having a memory array with a drain side and a source side, the method comprising:
- determining if a selected word line is closer to the drain side or the source side;
- and
- biasing unselected word lines with a first voltage if the selected word line is closer to the drain side, with a second voltage if the selected word line is closer to the source side, and with a third voltage if the selected word line is closer to a middle of the array between the source side and the drain side.
A method for reducing read failure in a memory device having a memory array with a drain side and a source side, the method comprising:
- determining a location of a selected word line between the drain side or the source side;
- and
- biasing unselected word lines with a pass read voltage that is different for each different location of the selected word line.
Dependencies are inferred from the claim text.