US 2010/0142283 A1 · PROGRAM METHOD WITH OPTIMIZED VOLTAGE LEVEL FOR FLASH MEMORY

Abstract

A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster on average program operation and a more accurate match of the subsequent increase in the programming voltage to the non-volatile memory device, the specific region or row being programmed and any changes due to device wear. In one embodiment of the present invention the manufacturing process/design and/or specific memory device is characterized by generating a failed bit percentage to programming voltage increase profile to set the desired programming voltage delta/increase. In another embodiment of the present invention, methods and apparatus are related for the programming of data into non-volatile memory devices and, in particular, NAND and NOR architecture Flash memory.

Claims18

Dependent claims

A memory device, comprising:

an array of non-volatile memory cells;
one or more sense amplifier circuits, wherein each of the one or more sense amplifier circuits comprises:
a plurality of data latches each coupled to the array of non-volatile memory cells and configured to latch a programmed state of one or more of the non-volatile memory cells in response to a read operation performed on the one or more non-volatile memory cells;
and
a plurality of cache latches, wherein each cache latch is configured to store data to be stored in the memory array during a program operation;
a first summation circuit coupled to the plurality of data latches and configured to generate a first summation of data stored in the plurality of data latches;
a second summation circuit coupled to the plurality of cache latches and configured to generate a second summation of data stored in the plurality of cache latches;
and
a program voltage adjustment circuit, wherein the program voltage adjustment circuit is configured to compare the first summation and the second summation and generate a program voltage change in response to a comparison of the first summation and the second summation.

6 more elements

A method of operating a memory device having an array of non-volatile memory cells, one or more sense amplifier circuits each having a plurality of data latches each coupled to the array of non-volatile memory cells and configured to latch a programmed state of one or more of the non-volatile memory cells in response to a read operation performed on the one or more non-volatile memory cells, and a plurality of cache latches, wherein each cache latch is configured to store data to be stored in the memory array during a program operation, comprising:

generating a first summation of data stored in the plurality of data latches using a first summation circuit coupled to the plurality of data latches;
generating a second summation of data stored in the plurality of cache latches using a second summation circuit coupled to the plurality of cache latches;
and
comparing the first summation and the second summation, and generating a program voltage change in response to a comparison of the first summation and the second summation, using a program voltage adjustment circuit.

1 more element

Dependencies are inferred from the claim text.

Program method with optimized voltage level for flash memory

Life of this patent

Program method with optimized voltage level for flash memory

Life of this patent

Abstract

Claims18