Nonvolatile semiconductor memory device having assist gate
AssigneeRenesas Technology Corp.
InventorsTakashi Kono, Yuichi Kunori, Hironori Iga
Life of this patent
Estimating the term…
Abstract
In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.
Claims6
1-25. (canceled)
A nonvolatile semiconductor memory device, comprising:
- a memory array portion, wherein
- said memory array portion is formed of a plurality of sub-blocks,
- each sub-block is formed of a plurality of word lines, a plurality of local bit lines which extend in the direction crossing the word lines, and a plurality of memory cells each storing information based on a level change of its threshold voltage and each placed so as to correspond to each intersection of a word line and a local bit line,
- said memory array portion further has a plurality of global bit lines which are provided so as to be shared in each sub-block,
- each global bit line includes a plurality of divided global bit lines which correspond to said plurality of sub-blocks respectively,
- each divided global bit line can be selectively connected to a divided global bit line which is adjacent in the direction in which it extends, and can be selectively connected to one local bit line within a corresponding sub-block,
- all of the connection means between the divided global bit lines are turned on, one of two adjacent global bit lines is connected to one local bit line within a selected sub-block, one of said two adjacent global bit lines is pre-charged to a first voltage prior to the read-out of data from a memory cell, and the other global bit line is pre-charged to a second voltage which is different from the first voltage at the time of read-out, and
- a read-out controlling circuit for reading out memory cell data by comparing the voltage of one of said two adjacent global bit lines to the second voltage of the other global bit line after a certain period of time has passed after the start of read-out from a memory cell, and after this voltage is changed in accordance with the memory cell data is further provided.
A nonvolatile semiconductor memory device, comprising
- a memory array portion, wherein
- said memory array portion is formed of a plurality of strings,
- each string is formed of a plurality of word lines, a plurality of local bit lines which extend in the direction crossing the word lines, and a plurality of memory cells each storing information based on a level change of its threshold voltage and each placed so as to correspond to each intersection of a word line and a local bit line,
- said memory array portion further has a plurality of global bit lines,
- each global bit line is shared by all of the strings and can be selectively connected to one local bit line within one string,
- one of said two adjacent global bit lines is pre-charged to a first voltage prior to the read-out of data from a memory cell and the other global bit line is pre-charged to a second voltage which is different from the first voltage at the time of read-out, and
- a read-out controlling circuit for reading out memory cell data by comparing the voltage of one of said two adjacent global bit lines to the second voltage of the other global bit line after a certain period of time has passed after the start of read-out from a memory cell, and after this voltage is changed in accordance with the memory cell data is further provided.
Dependencies are inferred from the claim text.