Page buffer circuit, nonvolatile memory device including the page buffer circuit, and method of operating the nonvolatile memory device

A nonvolatile memory device, comprising:

• a memory cell array comprising a number of memory blocks each including memory cells for storing data, the memory cells being coupled by a bit line and a word line;
• a page buffer unit, comprising page buffers coupled to the bit line and configured to include a plurality of latch circuits for latching data to be programmed into the memory cells or storing data from the memory cells, wherein each of the page buffers comprises a bit line control unit configured to temporarily charge a voltage of a bit line varying according to a program degree of memory cells when a program verification operation is performed and to provide the bit line with the charged voltage when a program operation for the bit line is performed;
• and
• a control unit configured to control a program, read, or erase operation, charge a voltage of a bit line according to a verification result to the page buffer when a program verification operation is performed using a double verification method, and apply the bit line with the voltage charged at the page buffer when a program operation is performed.

A method of operating a nonvolatile memory device, the method comprising:

• a first program step of performing a program operation using a first program voltage;
• a first verification step of performing a first verification operation on selected memory cells using a first verification voltage and temporarily charging a voltage of a bit line coupled to the selected memory cells;
• a second verification step of performing a second verification operation using a second verification voltage higher than the first verification voltage;
• a bit line voltage change step of, if a result of the second verification operation is not a pass, precharging the bit line in proportion to the temporarily charged voltage;
• and
• a second program step of performing a program operation using a second program voltage higher than the first program voltage by as much as a step voltage.

A page buffer circuit, comprising:

• a bit line selection unit configured to select a bit line coupled to memory cells;
• a latch unit configured to latch data to be programmed into the memory cells or store data from the memory cells through a sense node;
• and
• a bit line control unit configured to charge a voltage of the selected bit line in response to a charge control signal when a program verification operation is performed, and when a result of the program verification operation is a fail, re-execute the program verification operation by supplying the selected bit line with the charged voltage in response to a transfer control signal.