Programming methods for multi-level memory devices

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A method for programming a memory cell, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the memory cell having a threshold voltage selectively configurable into one of at least three programming states, the method comprising:

• generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region, the drain-to-source bias voltage comprising at least one voltage pulse;
• and
• generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, whereby the selected threshold voltage for each programming state is generated by applying a different selected gate voltage, wherein the selected gate voltage is ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the selected gate voltage being ramped with a ramping rate.

A method for programming a memory cell, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the memory cell having a threshold voltage selectively configurable into one of at least three programming states, the method comprising:

• generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region, the drain-to-source bias voltage comprising at least one voltage pulse;
• and
• injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, whereby a selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.

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