Memory employing redundant cell array of multi-bit cells
AssigneeSpansion LLC
InventorsKeiichiro Kikuchi, Norihiko Yamaki, Hiroaki Wada
Life of this patent
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Abstract
A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access.
Claims20
A memory, comprising:
- a plurality of core cell arrays of multi-bit memory cells;
- at least one redundant cell array;
- and
- a memory controller that is configured to dynamically assign the redundant cell array to a failed core cell array of at least a portion of the plurality of core cell arrays when erasing the portion of core cell arrays, wherein the memory controller is further configured to provide access to the redundant cell array when the failed core cell array is selected for read/write access.
A memory, comprising:
- a plurality of cell arrays of multi-bit memory cells, wherein each cell array of the plurality of cell arrays includes at least one dynamic reference cell;
- at least one redundant cell array;
- and
- a memory controller coupled to the plurality of cell arrays and the redundant cell array, wherein the memory controller is configured to perform actions, including:
- selecting a cell array from the plurality of cell arrays;
- reading a dynamic reference cell of the selected cell array;
- determining if a logic state of the dynamic reference cell indicates a failure state;
- and
- selecting the redundant cell array and providing read/write access to the redundant cell array based on the logic state.
A memory controller, comprising:
- a decoder circuit;
- and
- a controller circuit coupled to the decoder circuit, wherein the controller circuit is configured to perform actions, including:
- soft-programming a plurality of core cell arrays of multi-bit memory cells;
- under-erase verifying each core cell of the plurality of core cell arrays such that if a core cell exceeds a threshold voltage, the core cell array of the failed core cell is identified by writing a logic state to a corresponding dynamic reference cell.
Dependencies are inferred from the claim text.