Programming method to reduce gate coupling interference for non-volatile memory

A method of programming memory cells of a memory array, the method comprising:

• receiving first data to be written in a first memory cell;
• receiving second data to be written in a second memory cell, wherein the second memory cell is adjacent the first memory cell and where the first and the second data each corresponds to one of a plurality of programming levels to be programmed in the first and the second memory cells;
• determining a plurality of adjustment amounts, wherein each adjustment amount of the plurality of adjustment amounts corresponds to one of the plurality of programming levels;
• adjusting the first data by an adjustment amount corresponding to a programming level of the received second data;
• and
• programming the first memory cell with the adjusted first data prior to programming the second memory cell.

A method of compensating for programming interference effects in a memory device comprising an array of memory cells, the method comprising:

• characterizing a first coupling ratio between a first plurality of memory cells and a second plurality of memory cells of the array of memory cells where the first plurality of memory cells are adjacent the second plurality of memory cells in the array of memory cells;
• receiving first data to be programmed into the first plurality of memory cells;
• receiving second data to be programmed into the second plurality of memory cells;
• adjusting the first data to be programmed into each of the first plurality of memory cells by an amount dependent upon the second data to be programmed into an adjacent memory cell of the second plurality of memory cells and further dependent upon the first characterized coupling ratio;
• and
• programming the first plurality of memory cells with the adjusted first data prior to programming the second plurality of memory cells.

A method of programming memory cells of an array of memory cells, the method comprising:

• receiving a first data value to be programmed into a first memory cell, the first data value corresponding to a first range of threshold voltages;
• receiving a second data value to be programmed into a second memory cell, the second data value having a corresponding range of threshold voltages, and where the second memory cell is adjacent to the first memory cell;
• and
• programming the first memory cell to a first adjusted threshold voltage outside of the first range of threshold voltages to compensate for interference by the subsequent programming of the second data value into the second memory cell.