US 2010/0142246 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device comprises a plurality of memory cell mats, a plurality of sub-word driver regions and a plurality of sense amplifier regions, a plurality of intersection regions, a sub-amplifier, and a start signal (a control signal) supply circuit (a sub-amplifier control circuit). A plurality of sub-word driver regions and a plurality of sense amplifier regions are disposed adjacent to the plurality of memory cell mats. A plurality of intersection regions are intersection regions between the plurality of sub-word driver regions and the plurality of sense amplifier regions. The sub-amplifier is disposed in a first intersection region among the plurality of intersection regions. The start signal supply circuit is disposed in a second intersection region among the plurality of intersection regions, and supplies a start signal (a control signal) of the sub-amplifier to the sub-amplifier based on a sub-amplifier timing signal supplied from the extending direction of the sub-word driver region.

Claims14

Dependent claims

A semiconductor memory device comprising:

a plurality of memory cell mats;
a plurality of sub-word driver regions disposed adjacently to the memory cell mats and arranged along a first direction;
a plurality of sense amplifier regions disposed adjacently to the memory cell mats and arranged along a second direction substantially perpendicular to the first direction;
a plurality of intersection regions each disposed between corresponding adjacent ones of the sub-word driver regions and between corresponding adjacent ones of the sense amplifier regions, the plurality of intersection regions including a plurality of first regions and a plurality of second regions different from the first regions;
a plurality of sub-amplifiers disposed correspondingly in the first regions of the intersection regions;
and
a plurality of sub-amplifier control circuits each disposed in one of the second regions of the intersection regions, and each of the sub-amplifier control circuits supplying a control signal to corresponding one or ones of the sub-amplifiers based on a corresponding one of sub-amplifier timing signals supplied thereto from the first direction so as to activate the corresponding one or ones of the sub-amplifiers.

4 more elements

A device comprising:

a first memory area including a first memory cell array, a plurality of first sense amplifiers, and a plurality of first sub-amplifiers;
a second memory area including a second memory cell array, a plurality of second sense amplifiers, and a plurality of second sub-amplifiers;
and
a sub-amplifier control circuit disposed between the first and second memory areas, the sub-amplifier control circuit including a set of control signals which are elongated toward the first and second memory areas to control an operation of each of the first and second sub-amplifiers.

1 more element

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims14