Memory module and data input/output system
AssigneeHynix Semiconductor Inc.
InventorsKyung Hoon KIM, Sang Sic YOON
Life of this patent
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Abstract
A memory module is configured to include a first rank installed with a first memory chip and a second rank installed with a second memory chip. When the first and second memory chips are in a first data output mode, the first memory chip is configured to externally output lower order data of a plurality of data via lower data output pins. Also, when the first and second memory chips are in the first data output mode, the second memory chip is configured to externally output data that has the same order as the lower order data output by the first memory chip via upper data output pins.
Claims19
A memory module comprising:
- a first rank including a first memory chip;
- and
- a second rank including a second memory chip,
- wherein the first and second memory chips are configured to output a plurality of data and include first and second data output pins, and
- wherein, in a first data output mode:
- the first memory chip is configured to output, first data of the plurality of data via the first data output pins, wherein the first data is first order data, and
- the second memory chip is configured to output second data of the plurality of data via the second data output pins, wherein the second data is also first order data such that the data output from the first and second memory chips are of the same order.
A data input/output system comprising:
- a first memory module comprising a first rank to be installed with a first memory chip and a second rank to be installed with a second memory chip,
- wherein the first memory chip and the second memory chip are each configured to output data via a data output pins of a plurality of data output pins that are commonly connected to the first memory chip and the second memory chip, wherein the first and second memory chips are configured to output the respective data via data output pins that do not overlap;
- and
- a memory controller configured to commonly supply a chip selection signal to each of the first memory chip and the second memory chip in order to simultaneously activate the first memory chip and the second memory chip such that the first and second memory chips output the respective data via the non-overlapping data output pins.
A data input/output system comprising:
- a first memory module comprising a first rank to be installed with a first memory chip and a second rank to be installed with a second memory chip;
- a second memory module comprising a third rank to be installed with a third memory chip;
- and
- a memory controller configured to commonly supply a chip selection signal to each of the first memory chip and the third memory chip,
- wherein the first memory chip and the third memory chip are simultaneously activated according to the chip selection signal and are configured to output data via data output pins of the respective first and third memory chips.
A memory chip installed in a rank of a memory module that includes a single rank or a first and second rank, the memory chip comprising:
- a core configured to output a plurality of data, wherein the plurality of data includes first order data and second order data;
- a first data output logic unit configured to output the first order data via first data output pins according to a first activation control signal;
- a multiplexing unit configured to select and output one of the first order data and the second order data according to a multiplexing control signal;
- a second data output logic unit configured to output the output of the multiplexing unit via second data output pins according to a second activation control signal;
- and
- a control unit configured to generate the first activation control signal, the second activation control signal, and the multiplexing control signal according to rank information that identifies the rank of the memory chip and an output mode signal that designates a data output mode as being one of a first data output mode and a second data output mode.
Dependencies are inferred from the claim text.