Read and match circuit for low-voltage content addressable memory

Abstract

The present invention discloses a read and match circuit for a low-voltage content addressable memory, wherein the write circuit inputs the signals needing storing into the memory cells, and the read circuit retrieves the stored signals from the memory cells, and the match circuit compares the data stored in the memory cell with the data searched by the match circuit. As the circuits for writing, reading and matching are separated from each other and exempt from mutual interference, the present invention can achieve high reliability and low power consumption under a low-voltage operation environment without using a special fabrication process. In the present invention, the circuit is optimized to meet different requirements. The present invention enables the user to determine whether to have high speed or to have low power consumption. Further, the present invention can overcome the problems of current leakage and noise allowance in a low-voltage environment.

Dependencies are inferred from the claim text.