Bias circuit scheme for improved reliability in high voltage supply with low voltage device

A bias voltage generation circuit, comprising:

• a first resistive element connected to a first supply voltage and a first node;
• a second resistive element connected to said first node and a second node, said second node providing a first bias voltage;
• a third resistive element connected to said second node and a third node, said third node providing a second bias voltage;
• a fourth resistive element connected to said third node and a second supply voltage;
• a first field-effect transistor (FET) having a first gate, a first source, and a first drain, said first gate being connected to said third node, said first source being connected to an output that can exceed the first supply voltage, said first drain being connected to a fifth node;
• a second FET having a second gate, a second source, and a second drain, said second gate being connected to said first supply voltage, said second source being connected to said fifth node, said second drain being connected to a sixth node;
• and,
• a fifth resistive element connected to said sixth node and said third node.

A bias and output circuit, comprising:

• a supply voltage and a reference supply voltage;
• a first resistor connected between said supply voltage and a feedback node;
• a plurality of resistors connected in series between said feedback node and said reference supply voltage, said connections between said plurality of resistors defining a first bias voltage and a second bias voltage;
• a second resistor connected between said feedback node and a first drain node;
• a first field-effect transistor having a first gate node, said first drain node, and a first source node, said first gate node connected to said first supply voltage;
• a second field-effect transistor having a second gate node, a second drain node, and a second source node, said second drain node being connected to said first source node, said second gate node connected to said first bias voltage, and said second source node connected to an output signal node, said output signal node capable of experiencing an overshoot voltage;
• a third field-effect transistor having a third gate node, a third drain node, and a third source node, said third gate node connected to said first bias voltage and said third drain node connected to said output signal node;
• and,
• a fourth field-effect transistor having a fourth gate node, a fourth drain node, and a fourth source node, said fourth gate node connected to said second bias voltage, said fourth drain node connected to said output signal node.