Parallel-serial conversion circuit and data receiving system
AssigneeFujitsu Limited
InventorsYoshiyasu DOI, Hirotaka Tamura
Life of this patent
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Abstract
A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.
Claims16
A parallel-serial conversion circuit comprising:
- a plurality of data terminals each receiving a data signal;
- a selection circuit configured to select at least one of the data signals received through the plurality of data terminals;
- a first latch circuit configured to latch an output from the selection circuit based on a clock signal;
- a replica selection circuit configured to select one of a plurality of signals and output the selected signal;
- and
- a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.
A parallel-serial conversion circuit comprising:
- a latch circuit configured to operate in synchronization with a clock signal;
- a selector configured to select one of a plurality of first data signals and output the selected first data signal to the latch circuit;
- and
- a replica selection circuit configured to select one of a plurality of second data signals and output the selected second data signal,
- wherein a phase at the time when the first data signal is selected is adjusted based on the output from the replica selection circuit and the clock signal.
A data receiving system comprising:
- an interface circuit configured to externally receive a data signal;
- and
- an internal circuit configured to receive the data signal through the interface circuit,
- wherein the interface circuit includes a parallel-serial conversion circuit, and
- wherein the parallel-serial conversion circuit includes a plurality of data terminals each receiving a data signal;
- a selection circuit configured to select at least one of the data signals received through the plurality of data terminals;
- a first latch circuit configured to latch an output from the selection circuit based on a clock signal;
- a replica selection circuit configured to select one of a plurality of signals and output the selected signal;
- and
- a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.
Dependencies are inferred from the claim text.