Logic circuit, address decoder circuit and semiconductor memory

A logic circuit comprising:

• a first NAND gate that receives a first pulse signal and a first selection signal as inputs to output an inverted version of a logical product of the two input signals;
• a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal;
• a latch circuit that receives a second pulse signal and that latches an inverted version of the second pulse signal in response to an output signal of the first inverter gate;
• a second inverter gate that inverts an output signal of the latch circuit to output a resulting signal;
• a first PMOS transistor that has a drain connected to an output of the first NAND gate;
• has a gate connected to an output of the latch circuit and has a source connected to a power supply voltage;
• and
• a first NMOS transistor that has a drain connected to an output of the first inverter gate, has a gate connected to an output of the second inverter gate and has a source connected to a ground potential.

A logic circuit comprising:

• a first circuit that takes an inverted version of a logical product of a first signal supplied to a first input terminal and a second signal supplied to a second input terminal;
• a second circuit that receives an output signal of the first circuit to output an inverted version of the output signal at a first output terminal;
• a third circuit that takes an inverted version of a logical product of the second signal supplied to the second input terminal and a third signal supplied to a third input terminal;
• a fourth circuit that receives an output signal of the third circuit to output a signal which is an inverted version of the output signal at a second output terminal;
• a first switch element connected between an output of the first circuit and a first power supply, the first switch element being controlled to be on or off based on an output of the third circuit;
• and
• a second switch element connected between an output of the second circuit and a second power supply, the second switch element being controlled on or off based on an output of the fourth circuit.