Back to results
US 2010/0140801 A1Published application
Device
AssigneeElpida Memory, Inc.
InventorsSatoshi Anbai, Motoo Washiya
Life of this patent
Estimating the term…
Abstract
In a device acting as a semiconductor device, a first chip has a first protective layer pattern while a second chip has a second protective layer pattern which is two-dimensionally symmetrical with the first protective layer pattern to provide a reflection symmetrical relationship between the first and the second protective layer patterns. When the first and the second chips form a back-to-back structure, both the first and the second protective layer patterns are completely superposed with each other.
Claims9
A device, comprising:
- a first chip which comprises a first substrate having a first side and a second side opposite to the first side, a plurality of first bonding pads provide on the first side of the first substrate, and a plurality of first via hole conductors each extending from an associated one of the first bonding pads and penetrating the first substrate up to the second side of the first substrate;
- and
- a second chip which comprises a second substrate having a third side and a fourth side opposite to the third side, a plurality of second bonding pads provide on the third side of the second substrate, and a plurality of second via hole conductors each extending from an associated one of the second bonding pads and penetrating the second substrate up to the fourth side of the first substrate, the second bonding pads on the third side of the second substrate being arranged in a mirror symmetry to the first bonding pads on the first side of the first substrate;
- portions of the first via hole conductors appearing on the second side of the first substrate of the first chip being connected respectively portions of the second via hole conductors appearing on the fourth side of the second substrate of the second chip.
1 more element
A device comprising:
- a first and second chips each including a front surface and a back surface opposed to the front surface, the first and second chips adhering to each other so that the back surface of the first chip faces the back surface of the second chip;
- a first protective layer formed on the front surface of the first chip and including a plurality of first holes;
- a second protective layer formed on the front surface of the second chip and including a plurality of second holes, the second holes in the second protective layer being arranged in a mirror symmetry to the first holes in the first protective film;
- and
- a plurality of first via hole conductors each extending from a corresponding one of the first holes to a corresponding one of the second holes through the first and second chips.
2 more elements
Dependencies are inferred from the claim text.