Semiconductor chip bump connection apparatus and method
AssigneeATI Technologies ULC
InventorsRoden R. Topacio, Vincent Chan, Fan Yeung
Life of this patent
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Abstract
Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
Claims29
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An apparatus, comprising:
- a package substrate having a first side and plural conductor pads on the first side, each of the plural conductor pads having a first lateral dimension;
- a solder mask positioned on the first side of the substrate and having an opening co-located with each of the plural conductor pads, each of the openings having a second lateral dimension larger than the first lateral dimension;
- and
- a semiconductor chip having plural solder bumps coupled to a first side thereof, each of the plural solder bumps being metallurgically bonded to one of the plural conductor pads without an intervening conductor structure.
An apparatus, comprising:
- a package substrate having a first side and plural rectangular conductor pads on the first side, each of the plural conductor pads having a first lateral dimension;
- a solder mask positioned on the first side of the substrate and having a rectangular opening co-located with each of the plural conductor pads, each of the rectangular openings having a second lateral dimension larger than the first lateral dimension;
- and
- a semiconductor chip having plural solder bumps coupled to a first side thereof, each of the plural solder bumps being metallurgically bonded to one of the plural conductor pads without an intervening conductor structure.
An apparatus, comprising:
- a package substrate having a first side and plural conductor pads on the first side, each of the plural conductor pads having a first lateral dimension;
- a solder mask positioned on the first side of the substrate and having an opening co-located with each of the plural conductor pads, each of the openings having a second lateral dimension larger than the first lateral dimension;
- and
- a multi-core processor chip having plural solder bumps coupled to a first side thereof, each of the plural solder bumps being metallurgically bonded to one of the plural conductor pads without an intervening conductor structure.
Dependencies are inferred from the claim text.